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參數(shù)資料
| 型號： | 5962F1023301VXC |
| 元件分類： | 多路復(fù)用及模擬開關(guān) |
| 英文描述： | 16-CHANNEL, SGL ENDED MULTIPLEXER, CDFP28 |
| 封裝： | CERAMIC, DFP-28 |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 474K |
| 代理商： | 5962F1023301VXC |
15
Timing Diagrams
Multiplexer Asynchronous Parallel Timing (UT16MX110)
Multiplexer Synchronous Parallel Timing (UT16MX111)
Am Valid
CS
A[3:0]
S[x] = Analog Inputs
COM
(Previous)
COM = S[Am Valid]
COM = S[An Valid]
tAS1
VDD_IO
50%
GND
VDD_IO
50%
GND
tAS2
ApValid
COM = S[Ap Valid]
tAS1
HiZ
tMUX
tBBM
HiZ
tCYCLE
tPROP_D
AnValid
Note:
1. CS may be held in a continuous low state, holding CS high provides protection for false address change.
2. tCYCLE is the minimum cycle time between the falling edges of CS and/or any address changes. If tCYCLE is shorter than tPROP_D, an
addressing error may occur.
3. All bits (A[3:0]) of any address change should be received by the UT16MX110 within 18ns of the first bit change for proper operation.
tMUX
tBBM
tPROP_D
tMUX
tBBM
tPROP_D
Figure 5. UT16MX110 Timing Diagram
Figure 6. UT16MX111 Timing Diagram
Am Valid
PLATCH
A[3:0]
S[x] = Analog Inputs
COM(Previous)
COM = S[Am Valid]
COM = S[An Valid]
Note:
1. When PLATCH is in a high or low state, it provides protection for false address change.
2. tCYCLE must not be less than the maximum value of tPROP_D.
tLSU
VDD_IO
50%
GND
VDD_IO
50%
GND
tLHD
An Valid
tLSU
tLHD
tCYCLE
HiZ
tMUX
tBBM
tPROP_D
HiZ
tMUX
tBBM
tPROP_D
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