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參數(shù)資料
| 型號： | 5962F9581304V9X |
| 廠商： | INTERSIL CORP |
| 元件分類： | 多路復用及模擬開關(guān) |
| 英文描述： | DUAL 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, UUC13 |
| 封裝： | DIE-13 |
| 文件頁數(shù)： | 3/3頁 |
| 文件大?。?/td> | 88K |
| 代理商： | 5962F9581304V9X |
3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6411.1
July 7, 2008
Functional Diagram
Die Characteristics
DIE DIMENSIONS:
2690m x 5200m (106 milsx205 mils)
Thickness: 483m
± 25.4m (19 mils ± 1 mil)
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0k
± 1.0k
Top Metallization:
Type: AlSiCu
Thickness: 16.0k
± 2k
Substrate:
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish:
Silicon
ASSEMBLY RELATED INFORMATION:
Substrate Potential:
Unbiased (DI)
ADDITIONAL INFORMATION:
Worst Case Current Density:
<2.0 x 105 A/cm2
Transistor Count:
196
Metallization Mask Layout
HS-303ARH, HS-303BRH
N
P
IN
D
TRUTH TABLE
LOGIC
SW1 AND SW2
SW3 AND SW4
0OFF
ON
1ON
OFF
D3
D1
S1
IN1
GND
V-
D4
D2
S2
IN2
S3
V+
S4
HS-303ARH, HS-303BRH
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