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| 型號(hào)： | 5962R0722601VZA |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 12.5 us SETTLING TIME, 12-BIT DAC, CDSO10 |
| 封裝： | CERAMIC, SOIC-10 |
| 文件頁(yè)數(shù)： | 8/22頁(yè) |
| 文件大?。?/td> | 493K |
| 代理商： | 5962R0722601VZA |
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2.0 Applications Information
The simplicity of the DAC121S101 implies ease of use. How-
ever, it is important to recognize that any data converter that
utilizes its supply voltage as its reference voltage will have
essentially zero PSRR (Power Supply Rejection Ratio).
Therefore, it is necessary to provide a noise-free supply volt-
age to the device.
2.1 DSP/MICROPROCESSOR INTERFACING
Interfacing the DAC121S101 to microprocessors and DSPs
is quite simple. The following guidelines are offered to hasten
the design process.
2.1.1 ADSP-2101/ADSP2103 Interfacing
Figure 5 shows a serial interface between the DAC121S101
and the ADSP-2101/ADSP2103. The DSP should be set to
operate in the SPORT Transmit Alternate Framing Mode. It is
programmed through the SPORT control register and should
be configured for Internal Clock Operation, Active Low Fram-
ing and 16-bit Word Length. Transmission is started by writing
a word to the Tx register after the SPORT mode has been
enabled.
30018009
FIGURE 5. ADSP-2101/2103 Interface
2.1.2 80C51/80L51 Interface
A serial interface between the DAC121S101 and the
80C51/80L51 microcontroller is shown in Figure 6. The
SYNC signal comes from a bit-programmable pin on the mi-
crocontroller. The example shown here uses port line P3.3.
This line is taken low when data is to transmitted to the
DAC121S101. Since the 80C51/80L51 transmits 8-bit bytes,
only eight falling clock edges occur in the transmit cycle. To
load data into the DAC, the P3.3 line must be left low after the
first eight bits are transmitted. A second write cycle is initiated
to transmit the second byte of data, after which port line P3.3
is brought high. The 80C51/80L51 transmit routine must rec-
ognize that the 80C51/80L51 transmits data with the LSB first
while the DAC121S101 requires data with the MSB first.
30018010
FIGURE 6. 80C51/80L51 Interface
2.1.3 68HC11 Interface
A serial interface between the DAC121S101 and the 68HC11
microcontroller is shown in Figure 7. The SYNC line of the
DAC121S101 is driven from a port line (PC7 in the figure),
similar to the 80C51/80L51.
The 68HC11 should be configured with its CPOL bit as a zero
and its CPHA bit as a one. This configuration causes data on
the MOSI output to be valid on the falling edge of SCLK. PC7
is taken low to transmit data to the DAC. The 68HC11 trans-
mits data in 8-bit bytes with eight falling clock edges. Data is
transmitted with the MSB first. PC7 must remain low after the
first eight bits are transferred. A second write cycle is initiated
to transmit the second byte of data to the DAC, after which
PC7 should be raised to end the write sequence.
30018011
FIGURE 7. 68HC11 Interface
2.1.4 Microwire Interface
Figure 8 shows an interface between a Microwire compatible
device and the DAC121S101. Data is clocked out on the rising
edges of the SCLK signal.
30018012
FIGURE 8. Microwire Interface
2.2 USING REFERENCES AS POWER SUPPLIES
Recall the need for a quiet supply source for devices that use
their power supply voltage as a reference voltage.
Since the DAC121S101 consumes very little power, a refer-
ence source may be used as the supply voltage. The advan-
tages of using a reference source over a voltage regulator are
accuracy and stability. Some low noise regulators can also be
used for the power supply of the DAC121S101. Listed below
are a few power supply options for the DAC121S101.
2.2.1 LM4130
The LM4130 reference, with its 0.05% accuracy over tem-
perature, is a good choice as a power source for the
DAC121S101. Its primary disadvantage is the lack of 3 V and
5 V versions. However, the 4.096 V version is useful if a 0 to
4.095 V output range is desirable or acceptable. Bypassing
the LM4130 VIN pin with a 0.1 F capacitor and the VOUT
pin with a 2.2 F capacitor will improve stability and reduce
output noise. The LM4130 comes in a space-saving 5-pin
SOT23.
30018013
FIGURE 9. The LM4130 as a power supply
www.national.com
16
DAC121S101QML
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| 5962R0722701VZA | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 8-Ch 50 kSPS-1 MSPS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| 5962R0722902VXA | 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| 5962R0722961VXA | 功能描述:低壓差穩(wěn)壓器 - LDO 3-Terminal Adj Reg RoHS:否 制造商:Texas Instruments 最大輸入電壓:36 V 輸出電壓:1.4 V to 20.5 V 回動(dòng)電壓（最大值）:307 mV 輸出電流:1 A 負(fù)載調(diào)節(jié):0.3 % 輸出端數(shù)量: 輸出類型:Fixed 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-20 |
| 5962R0724902VPC | 制造商:Intersil Corporation 功能描述: |
| 5962R0724904VPC | 制造商:Intersil Corporation 功能描述: |
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