參數(shù)資料
型號(hào)： 5962R1023605VXC
元件分類： 多路復(fù)用及模擬開關(guān)
英文描述： 16-CHANNEL, DIFFERENTIAL MULTIPLEXER, CDFP28
封裝： CERAMIC, FLATPACK-28
文件頁(yè)數(shù)： 4/22頁(yè)
文件大?。?/td> 176K
代理商： 5962R1023605VXC
12
DIGITAL TIMING CHARACTERISTICS (UT16MX114)1
(VDD=3.3V; -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered
Notes:
1. For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019,
Condition A up to the maximum TID level procured (see ordering information).
2. Device is production tested with RL=50 Ohm. The device is characterized with RL=500Ohm.
3. A minimum of RL=500 Ohm is needed to guarantee performance continuous DC operation for a 15 yr. lifetime.
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Asynchronous Parallel Interface (UT16MX114)
AVDD
AVSS
tPROP_S
Propagation delay of analog input
(S[15:0] to analog output (COM).2,3
RL=500 Ohm
CL=50pF
5.0
0V
31
ns
tPROP_D
Propagation delay of digital input
(A[3:0], CS, PLATCH, SS) to analog
output (COM).
RL=1k Ohm
CL=50pF
See Figure 5.
5.0
0V
31
135
ns
tMUX
Mux decoding time
RL=1k Ohm
CL=50pF
See Figure 5.
5.0
0V
13
50
ns
tBBM
Break-Before-Make-Delay
RL=1k Ohm
CL=50pF
See Figure 5.
5.0
0V
21
86
ns
tPZLH
Output enable time from HiZ to Low or
High once RESET is pulled low.
RL=1k Ohm
CL=50pF
See Figure 8.
5.0
0V
90
ns
tPLHZ
Output disable time from Low or High
to HiZ once RESET is pulled high.
RL=1k Ohm
CL=50pF
See Figure 8.
5.0
0V
50
ns
tLSU
The minimum amount of time that the
addresses should be set before the rising
edge of PLATCH.
See Figure 5.
5
ns
tLHD
The minimum amount of time that the
addresses should be held after the rising
edge of PLATCH.
See Figure 5.
10
ns
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