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參數(shù)資料
| 型號： | 5962R1023606VXC |
| 元件分類： | 多路復用及模擬開關 |
| 英文描述： | 16-CHANNEL, DIFFERENTIAL MULTIPLEXER, CDFP28 |
| 封裝： | CERAMIC, FLATPACK-28 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 176K |
| 代理商： | 5962R1023606VXC |
13
DIGITAL TIMING CHARACTERISTICS (UT16MX115)1
(VDD=3.3V; -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Serial Interface (UT16MX115)
AVDD
AVSS
tPROP_S
Propagation delay of analog input
(S[15:0] to analog output (COM).2,3
RL=500 Ohm
CL=50pF
5.0
0V
31
ns
tPROP_D
Propagation delay of digital input
(A[3:0], CS, PLATCH, SS) to analog
output (COM).
RL=1k Ohm
CL=50pF
See Figure 6.
5.0
0V
31
135
ns
tMUX
Mux decoding time.
RL=1k Ohm
CL=50pF
See Figure 6.
5.0
0V
13
50
ns
tBBM
Break-Before-Make-Delay
RL=1k Ohm
CL=50pF
See Figure 6.
5.0
0V
21
86
ns
tPZLH
Output enable time from HiZ to Low or
High once RESET is pulled low.
RL=1k Ohm
CL=50pF
See Figure 8.
5.0
0V
90
ns
tPLHZ
Output disable time from Low or High
to HiZ once RESET is pulled high.
RL=1k Ohm
CL=50pF
See Figure 8.
5.0
0V
50
ns
fSCLK
SCLK frequency
See Figure 6.
2
MHz
tH
SCLK high time
See Figure 6.
190
ns
tL
SCLK low time
See Figure 6.
190
ns
tSSU
First SCLK setup time (for shifting
window)
See Figure 6.
5
ns
tSSH
Last SCLK hold time (for shifting
window)
See Figure 6.
10
ns
tSU
The minimum amount of time that the
Data In (MOSI) should be set before the
rising edge of SCLK.
See Figure 6.
3
ns
tHD
The minimum amount of time that the
Data In (MOSI) should be held after the
falling edge of SCLK.
See Figure 6.
5
ns
tDO
Data Out (MISO) valid (after falling
edge of SLCK)
See Figure 6.
22
ns
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