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參數(shù)資料
| 型號： | 5962R1121306VXC |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, CDFP8 |
| 封裝： | ROHS COMPLIANT, CERAMIC, FLAT PACK-8 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 1068K |
| 代理商： | 5962R1121306VXC |
ISL705ARH, ISL705BRH, ISL705CRH, ISL706ARH, ISL706BRH, ISL706CRH
15
FN7662.0
September 15, 2011
Package Outline Drawing
K8.A
8 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 2, 12/10
LEAD FINISH
SIDE VIEW
TOP VIEW
-D-
-C-
0.265 (6.75)
0.115 (2.92)
0.026 (0.66)
0.265 (6.73)
SEATING AND
0.180 (4.57)
0.03 (0.76) MIN
BASE PLANE
-H-
0.09 (0.23)
0.005 (0.13)
PIN NO. 1
ID AREA
0.050 (1.27 BSC)
0.022 (0.56)
0.015 (0.38)
MIN
0.245 (6.22)
0.070 (1.18)
0.170 (4.32)
0.370 (9.40)
0.250 (6.35)
0.04 (0.10)
0.245 (6.22)
1.
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
2.
of the tab dimension do not apply.
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4.
5.
shall be molded to the bottom of the package to cover the leads.
6.
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7.
8.
NOTES:
0.015 (0.38)
0.008 (0.20)
PIN NO. 1
ID OPTIONAL
1
2
4
6
3
Dimensioning and tolerancing per ANSI Y14.5M - 1982.
Controlling dimension: INCH.
Index area: A notch or a pin one identification mark shall be located
If a pin one identification mark is used in addition to a tab, the limits
Measure dimension at all four corners.
For bottom-brazed lead packages, no organic or polymeric materials
Dimension shall be measured at the point of exit (beyond the
SECTION A-A
BASE
METAL
0.007 (0.18)
0.004 (0.10)
0.009 (0.23)
0.004 (0.10)
0.019 (0.48)
0.015 (0.38)
0.0015 (0.04)
MAX
0.022 (0.56)
0.015 (0.38)
0.045 (1.14)
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