VERSACLOCK LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
參數(shù)資料
型號(hào): 5P49EE802NDGI
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 2/26頁(yè)
文件大?。?/td> 0K
描述: IC CLOCK GENERATOR 28QFN
標(biāo)準(zhǔn)包裝: 75
系列: VersaClock™
類型: 時(shí)鐘發(fā)生器
PLL: 帶旁路
輸入: LVTTL,晶體
輸出: LVCMOS,LVTTL
電路數(shù): 1
比率 - 輸入:輸出: 2:7
差分 - 輸入:輸出: 無(wú)/是
頻率 - 最大: 120MHz
除法器/乘法器: 是/無(wú)
電源電壓: 1.71 V ~ 1.89 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 28-VFQFPN(4x4)
包裝: 管件
其它名稱: 800-2523
IDT5P49EE802
VERSACLOCK LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
IDT VERSACLOCK LOW POWER CLOCK GENERATOR
10
IDT5P49EE802
REV M 072512
SEL[1:0] Function
The IDT5P49EE802 can support up to three unique
configurations. Users may pre-program all configurations,
selected using SEL[1:0] pins. Alternatively, users may use
I2C interface to configure these registers on- the-fly.
Always power with SEL1=1 and/or SEL0=1.
Power Down/Sleep Mode is selected by the No_PD bit.
No_PD=0 enables Power Down mode with no outputs.
No_PD=1 enables sleep mode with 32kHz output on OUT2.
.
Configuration OUTx IO Standard
Users can configure the individual output IO standard from
a single 3.3V power supply. Each output can support 1.8V/
2.5V or 3.3V LVCMOS. VDDO1 must have the highest
voltage of any pin on the device. VDDO2 and VDDO3 may
have any value between 1.8V and VDDO1.
Programming the Device
I2C may be used to program the IDT5P49EE802.
– Device (slave) address = 7'b1101010
I2C Programming
The IDT5P49EE802 is programmed through an I2C-Bus
serial interface, and is an I2C slave device. The read and
write transfer formats are supported. The first byte of data
after a write frame to the correct slave address is interpreted
as the register address; this address auto-increments after
each byte written or read.
The frame formats are shown in the following illustration.
Framing
First Byte Transmitted on I2C Bus
SEL1
SEL0
Configuration Selections
0
Power Down/Sleep Mode
0
1
Select CONFIG0
1
0
Select CONFIG1
1
Select CONFIG2
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