參數(shù)資料
型號(hào)： 635L5I3FREQ
廠商： CTS CORP
元件分類： XO, clock
英文描述： CRYSTAL OSCILLATOR, CLOCK, 19.44 MHz - 250 MHz, LVDS OUTPUT
封裝： GREEN, CERAMIC PACKAGE-6
文件頁數(shù)： 2/4頁
文件大?。?/td> 153K
代理商： 635L5I3FREQ
Document No. 008-0284-0
Page 2 - 4
Rev. D
CTS Electronic Components, Inc. 171 Covington Drive Bloomingdale, IL 60108
Model 635
7.5x5.0mm Low Cost
LVPECL or LVDS Clock Oscillator
ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Maximum Supply Voltage
VCC
-
-0.5
-
5.0
V
Storage Temperature
TSTG
-
-55
-
125
°C
Frequency Range (See Note 1)
LVPECL and LVDS
19.44
-
250
Frequency Stability
(See Note 2 and Ordering Information)
f/fO
--
-
20, 25, 50
or 100
± ppm
Operating Temperature
Commercial
-20
70
Industrial
-40
85
2.38
2.5
2.63
3.14
3.3
3.47
Supply Current
LVPECL
-
50
100
LVDS
-
25
60
Start Up Time
TS
Application of VCC
-3
5
ms
Phase Jitter
tjrms
Bandwidth 12 kHz - 20 MHz
-
1
ps RMS
Period Jitter
pjrms
-
5
ps RMS
Enable Function
Standby
Enable Input Voltage
VIH
Pin 1 or Pin 2 Logic '1', Output Enabled
0.7*VCC
--
V
Disable Input Voltage
VIL
Pin 1 or Pin 2 Logic '0', Output Disabled
-
0.3*VCC
Disable Current
IIL
Pin 1 or Pin 2 Logic '1' , Output Disabled
-
20
uA
Enable Time
TPLZ
Pin 1 or Pin 2 Logic '1'
--
5
ns
LVPECL WAVEFORM
Output Load
RL
--
50
-
Ohms
Output Duty Cycle
SYM
@ VCC - 1.3V
45
-
55
%
Output Voltage Levels
Logic '1' Level
VOH
PECL Load
VCC - 1.025V
--
Logic '0' Level
VOL
PECL Load
-
VCC - 1.62V
Rise and Fall Time
fO < 100 MHz
-0.8
1.0
fO > 100 MHz
-0.5
0.6
LVDS WAVEFORM
Output Load
RL
Between Outputs
-
100
-
Ohms
Output Duty Cycle
SYM
@ 1.25V
45
-
55
%
Differential Output Voltage
VOD
RL = 100 Ohms
247
350
454
mV
Differential Output Error
-
50
mV
Offset Voltage
VOS
LVDS Load
1.125
1.25
1.375
V
Offset Error
-
50
mV
Output Voltage Levels
Logic '1' Level
VOH
LVDS Load
-
1.43
1.6
Logic '0' Level
VOL
LVDS Load
0.9
1.1
-
Rise and Fall Time
fO < 100 MHz
-0.8
1.0
fO > 100 MHz
-0.5
0.6
Notes:
1.
2.
Absolu
te
Max
im
u
m
s
fO
-MHz
TA
-°C
25
Ele
ct
rical
an
d
Wave
fo
rm
P
a
ra
m
et
er
s
@ 20% - 80% Levels
mA
V
For frequencies above 160 MHz consult factory for availability.
TR, TF
@ 20% - 80% Levels
ns
Inclusive of initial tolerance at time of shipment, changes in supply voltage, load, temperature and 10 year aging.
VCC
± 5 %
TR, TF
Maximum Load
ns
Supply Voltage
ICC
V
PECL/LVDS OUTPUT WAVEFORM
Tr
Tf
UPTIME (t)
PERIOD (T)
80%
50%
20%
DUTY CYCLE = t/T x 100 (%)
OUT
OH
V
OL
V
VOS
ENABLE TRUTH TABLE
PIN 1 or PIN 2
PIN 4 / PIN 5
Logic ‘1’
Output
Open
Output
Logic ‘0’
High Imp.
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