參數(shù)資料
型號: 70V3319S133BCGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 256K X 18 DUAL-PORT SRAM, 4.2 ns, CBGA256
封裝: 17 X 17 MM X 1.4 MM, 1 MM PITCH, GREEN, BGA-256
文件頁數(shù): 13/23頁
文件大?。?/td> 222K
代理商: 70V3319S133BCGI
6.42
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
20
JTAG AC Electrical
Characteristics(1,2,3,4)
70V3319/99
Symbol
Parameter
Min.
Max.
Units
tJCYC
JTAG Clock Input Period
100
____
ns
tJCH
JTAG Clock HIGH
40
____
ns
tJCL
JTAG Clock Low
40
____
ns
tJR
JTAG Clock Rise Time
____
3
(1)
ns
tJF
JTAG Clock Fall Time
____
3
(1)
ns
tJRST
JTAG Reset
50
____
ns
tJRSR
JTAG Reset Recovery
50
____
ns
tJCD
JTAG Data Output
____
25
ns
tJDC
JTAG Data Output Hold
0
____
ns
tJS
JTAG Setup
15
____
ns
tJH
JTAG Hold
15
____
ns
5623 tbl 12
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
JTAG Timing Specifications
TCK
Device Inputs(1)/
TDI/TMS
Device Outputs(2)/
TDO
TRST
tJCD
tJDC
tJRST
tJS
tJH
tJCYC
tJRSR
tJF
tJCL
tJR
tJCH
5623 drw 21
,
Figure 5. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
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