參數(shù)資料
型號: 70V657S12BFG8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: 32K X 36 DUAL-PORT SRAM, 12 ns, PBGA208
封裝: 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FPBGA-208
文件頁數(shù): 10/24頁
文件大?。?/td> 316K
代理商: 70V657S12BFG8
IDT70V659/58/57S
High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
18
Truth Table III — Interrupt Flag(1,4)
Waveform of Interrupt Timing(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. Refer to Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. INTL and INTR must be initialized at power-up.
5. A16x is a NC for IDT70V658, therefore Interrupt Addresses are FFFF and FFFE.
6. A16x and A15x are NC's for IDT70V657, therefore Interrupt Addresses are 7FFF and 7FFE.
4869 drw 16
ADDR"A"
INTERRUPT SET ADDRESS
CE"A"
R/
W"A"
tAS
tWC
tWR
(3)
(4)
tINS
(3)
INT"B"
(2)
4869 drw 17
ADDR"B"
INTERRUPT CLEAR ADDRESS
CE"B"
OE"B"
tAS
tRC
(3)
tINR
(3)
INT"B"
(2)
Left Port
Right Port
Function
R/WL
CEL
OEL
A16L-A0L(5,6)
INTL
R/WR
CER
OER
A16R-A0R(5,6)
INTR
L
X
1FFFF
XXXX
X
L(2)
Set Right INTR Flag
X
XXX
X
L
1FFFF
H(3)
Reset Right INTR Flag
XX
X
L(3)
L
X
1FFFE
X
Set Left INTL Flag
X
L
1FFFE
H(2)
X
Reset Left INTL Flag
4869 tbl 16
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