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參數(shù)資料
| 型號： | 70V9389L9PRFI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 64K X 18 DUAL-PORT SRAM, 20 ns, PQFP128 |
| 封裝： | TQFP-128 |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 211K |
| 代理商： | 70V9389L9PRFI8 |
6.42
14
IDT70V9389/289L
High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
TimingWaveform of Flow-ThroughRead-to-Write-to-Read(OEControlled)(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3.
CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since
ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
DATAIN
Dn + 2
CE0
CLK
4856 drw 12
Qn
DATAOUT
CE1
UB, LB
tCD1
Qn + 1
tCH1
tCL1
tCYC1
tSD tHD
tCD1
tDC
tCKHZ
Qn + 3
tCD1
tDC
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
READ
NOP
READ
tCKLZ
(4)
(2)
(1)
tSW tHW
WRITE
(5)
R/W
ADDRESS
An
An +1
An + 2
An + 3
An + 4
An + 5
(4)
DATAIN
Dn + 2
CE0
CLK
4856 drw 13
Qn
DATAOUT
CE1
UB, LB
tCD1
tCH1
tCL1
tCYC1
tSD tHD
tCD1
tDC
tCD1
tDC
tSC
tHC
tSB
tHB
tSW tHW
tSA
tHA
READ
WRITE
READ
tCKLZ
(2)
Dn + 3
tOHZ
(1)
tSW tHW
OE
tOE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT70V9289L9PRF8 | 64K X 16 DUAL-PORT SRAM, 20 ns, PQFP128 |
| 710026-3 | 25 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL |
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| 710027-2 | 35 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL |
| 710027-1 | 35 mm2, COPPER ALLOY, TIN FINISH, WIRE TERMINAL |
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