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參數(shù)資料
| 型號(hào)： | 71117 |
| 廠商： | Vishay Intertechnology,Inc. |
| 英文描述： | SI9113 Demonstration Board |
| 中文描述： | SI9113演示板 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 201K |
| 代理商： | 71117 |
Si9113DB
Vishay Siliconix
Document Number: 71117
29-Feb-00
www.siliconix.com FaxBack 408-970-5600
3
Output Regulation
The output regulation of slave outputs depend upon the
loading condition of main output.
In Si9113D1, the V
OUT1
(3.3 V) is tightly regulated to within 1%,
while V
OUT2
(40 V) follows the main output. Figure 2 depicts
the typical load regulation of 40 V output, when the main output
is at 10% and at full load condition.
In Si9113D2, the V
OUT1
and V
OUT2
are both moderately
regulated. Figures 3 and 4 show the 3.3-V and 40-V regulation
with the outputs loaded at 10% to100% of the rated load. The
output voltages are essentially constant with respect to any
variation of input voltage in case of both demo boards.
Output Ripple and Noise
The tantalum chip capacitors are used for lower ESR and
higher ripple current capability. Low cost aluminium capacitors
can also be used where form fator and/or output ripple are of
secondary importance. Also, a small additional LC filter can be
added at 3.3-V output for further attenuation of ac component
by even five to ten times. The Si9113D1 – Figure 5 and
Si9113D2 – Figure 6 show the ripple at a full load and 48-V
input.
(
V
O
3.140
3.180
3.220
3.260
3.300
3.340
3.380
3.420
3.460
0
25
50
75
100
125
150
FIGURE 3.
V
OUT1
(3.3 V) Load/cross Regulation – Si9113D2
40 V @ 1.2 mA
40 V @ 12 mA
I
OUT1
(mA)
38.00
38.50
39.00
39.50
40.00
40.50
41.00
41.50
42.00
0
3.00
6.00
9.00
12.00
15.00
FIGURE 4.
V
OUT2
(40 V) Load/Cross Regulation – Si9113D2
3.3 V @ 12 mA
I
OUT2
(mA)
V
3.3 V @ 120 mA
V
= 48 V
Outputs = At Full Load
Ch1 = 3.3 V (20 mV/div))
Ch3 = 40 V (100 mV/div)
FIGURE 5.
Output Ripple and Noise – Si9113D1
V
= 48 V
Outputs = At Full Load
Ch1 = 3.3 V (20 mV/div))
Ch3 = 40 V (100 mV/div)
FIGURE 6.
Output Ripple and Noise – Si9113D2
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