參數(shù)資料
型號： 71M6521DE-IMR/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, QCC68
封裝： LEAD FREE, LQFN-68
文件頁數(shù)： 22/103頁
文件大?。?/td> 1691K
代理商： 71M6521DE-IMR/F
71M6521DE/71M6521FE
Energy Meter IC
DATA SHEET
OCTOBER 2010
v1.1
2005-2010 Teridian Semiconductor Corporation
Page: 25 of 103
A Maxim Integrated Products Brand
19-5370; 10/10
MSB
LSB
SM
-
SM21
REN1
TB81
RB81
TI1
RI1
Table 16: The S1CON register
Bit
Symbol
Function
S0CON.7
SM0
These two bits set the UART0 mode:
Mode
Description
SM0
SM1
0
N/A
0
1
8-bit UART
0
1
2
9-bit UART
1
0
3
9-bit UART
1
S0CON.6
SM1
S0CON.5
SM20
Enables the inter-processor communication feature.
S0CON.4
REN0
If set, enables serial reception. Cleared by software to disable reception.
S0CON.3
TB80
The 9
th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU, depending
on the function it performs (parity check, multiprocessor communication etc.)
S0CON.2
RB80
In modes 2 and 3 it is the 9
th data bit received. In Mode 1, if SM20 is 0, RB80 is the
stop bit. In mode 0 this bit is not used. Must be cleared by software
S0CON.1
TI0
Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be
cleared by software.
S0CON.0
RI0
Receive interrupt flag, set by hardware after completion of a serial reception. Must
be cleared by software
Table 17: The S0CON Bit Functions
Bit
Symbol
Function
S1CON.7
SM
Sets the baud rate for UART1
SM
Mode
Description
Baud Rate
0
A
9-bit UART
variable
1
B
8-bit UART
variable
S1CON.5
SM21
Enables the inter-processor communication feature.
S1CON.4
REN1
If set, enables serial reception. Cleared by software to disable reception.
S1CON.3
TB81
The 9
th transmitted data bit in Mode A. Set or cleared by the MPU, depending on the
function it performs (parity check, multiprocessor communication etc.)
S1CON.2
RB81
In Modes A and B, it is the 9
th data bit received. In Mode B, if SM21 is 0, RB81 is the
stop bit. Must be cleared by software
S1CON.1
TI1
Transmit interrupt flag, set by hardware after completion of a serial transfer. Must be
cleared by software.
S1CON.0
RI1
Receive interrupt flag, set by hardware after completion of a serial reception. Must
be cleared by software
Table 18: The S1CON Bit Functions
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