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| 型號(hào)： | 71M6533-IGTR/F |
| 廠商： | TERIDIAN SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQFP100 |
| 封裝： | LEAD FREE, LQFP-100 |
| 文件頁(yè)數(shù)： | 42/124頁(yè) |
| 文件大?。?/td> | 2008K |
| 代理商： | 71M6533-IGTR/F |
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71M6533/71M6534 Data Sheet
FDS_6533_6534_004
24
2007-2009 TERIDIAN Semiconductor Corporation
v1.1
Stack Pointer (SP):
The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before
PUSH and CALL instructions, causing the stack to begin at location 0x08.
Data Pointer:
The data pointer (DPTR) is 2 bytes wide. The lower part is DPL, and the highest is DPH. It can be loaded
as two registers (e.g. MOV DPL,#data8). It is generally used to access external code or data space (e.g.
MOVC A,@A+DPTR or MOVX A,@DPTR respectively).
Program Counter:
The program counter (PC) is 2 bytes wide and initialized to 0x0000 after reset. This register is incre-
mented when fetching operation code or when operating on data from program memory.
Port Registers:
The I/O ports are controlled by Special Function Registers P0, P1 and P2. The contents of the SFR can
be observed on corresponding pins on the chip. Writing a 1 to any of the ports (see Table 12) causes the
corresponding pin to be at high level (V3P3). Writing a 0 causes the corresponding pin to be held at a
low level (GND). The data direction registers DIR0, DIR1, and DIR2 define individual pins as input or out-
put pins (see Section 1.4.7 Digital I/O for details).
Table 12: Port Registers
Register
SFR Ad-
dress
R/W
Description
P0
0x80
R/W
Register for port 0 read and write operations.
DIR0
0xA2
R/W
Data direction register for port 0. Setting a bit to 1 means that the corres-
ponding pin is an output.
P1
0x90
R/W
Register for port 1 read and write operations.
DIR1
0x91
R/W
Data direction register for port 1.
P2
0xA0
R/W
Register for port 2 read and write operations.
DIR2
0xA1
R/W
Data direction register for port 2.
All DIO ports on the chip are bi-directional. Each of them consists of a Latch (SFR P0 to P2), an output
driver and an input buffer, therefore the MPU can output or read data through any of these ports. Even if
a DIO pin is configured as an output, the state of the pin can still be read by the MPU, for example when
counting pulses issued via DIO pins that are under CE control.
The technique of reading the status of or generating interrupts based on DIO pins configured as
outputs can be used to implement pulse counting.
Clock Stretching (CKCON)
The three low order bits of the CKCON register define the stretch memory cycles that are used for
MOVX instructions when accessing external peripherals. The practical value of this register for the
71M6533/71M6534 is to guarantee access to XRAM between CE, MPU, and SPI. The default setting of
CKCON (001) should not be changed.
Table 13 shows how the signals of the External Memory Interface change when stretch values are set
from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the
CKCON register (001), which is shown in bold in the table, performs the MOVX instructions with a stretch
value equal to 1.
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