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參數(shù)資料
| 型號(hào)： | 71V2556XSA166BGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 128K X 36 ZBT SRAM, PBGA119 |
| 封裝： | GREEN, BGA-119 |
| 文件頁數(shù)： | 7/23頁 |
| 文件大?。?/td> | 350K |
| 代理商： | 71V2556XSA166BGI8 |
6.42
IDT71V2556, 128K x 36, 3.3V Synchronous ZBT SRAMs
with 2.5V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
15
Timing Waveform of Read Cycle(1,2,3,4)
NOTES:
1.
Q
(A
1)
represents
the
first
output
from
the
external
address
A
1.
Q
(A
2)
represents
the
first
output
from
the
external
address
A
2;
Q
(A
2+1
)represents
the
next
output
data
in
the
burst
sequence
of
the
base
address
A
2,
etc.
where
address
bits
A0
and
A1
are
advancing
for
the
four
word
burst
in
the
sequence
defined
by
the
state
of
the
LBO
input.
2.
C
E
2timing
transitions
are
identical
but
inverted
to
the
CE
1and
CE
2
signals.
For
example,
when
CE
1and
CE
2are
LOW
on
this
waveform,
CE
2is
HIGH.
3.
Burst
ends
when
new
address
and
control
are
loaded
into
the
SRAM
by
sampling
ADV/
LD
LOW.
4.
R
/W
is
don't
care
when
the
SRAM
is
bursting
(ADV/
LD
sampled
HIGH).
The
nature
of
the
burst
access
(Read
or
Write)
is
fixed
by
the
state
of
the
R/
W
signal
when
new
address
and
control
are
loaded
into
the
SRAM.
ADV/
LD
(CEN
high,
eliminates
current
L-H
clock
edge)
O2(A2)
tCD
tHADV
Pipeline
Read
(Burst
Wraps
around
to
initial
state)
tCDC
tCLZ
tCHZ
tCD
tCDC
R/
W
CLK
CEN
ADDRESS
OE
DATA
OUT
tHE
tSE
A1
A2
O1(A2)
tCH
tCL
tCYC
tSADV
tHW
tSW
tHA
tSA
tHC
tSC
Burst
Pipeline
Read
Pipeline
Read
BW
1
-
BW
4
4875
drw
06
CE
1
,
CE
2
(2)
Q(A
2+3
)
Q(A
2
)
Q(A
2+2
)
Q(A
2+2
)
Q(A
2+1
)
Q(A
2
)
Q(A
1
)
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