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參數(shù)資料
| 型號： | 71V35781S183PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 256K X 18 CACHE SRAM, 3.3 ns, PQFP100 |
| 封裝： | 14 X 20 MM, PLASTIC, TQFP-100 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大小： | 632K |
| 代理商： | 71V35781S183PF |
6.42
16
IDT71V35761, IDT71V35781, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 - Byte Controlled(1,2,3)
NOTES:
1
.
ZZ
input
is
LOW,
GW
is
HIGH
and
LBO
is
Don't
Care
for
this
cycle.
2.
O4
(Aw)
represents
the
final
output
data
in
the
burst
sequence
of
the
base
address
Aw.
I1
(Ax)
represents
the
first
input
fr
om
the
external
address
Ax.
I1
(Ay)
represents
the
first
input
from
the
external
address
Ay;
I2
(Ay)
represents
the
next
input
data
in
the
burst
sequence
of
the
base
address
Ay,
etc.
where
A0
and
A1
are
advan
cing
for
the
four
word
burst
in
the
sequence
defined
by
the
state
of
the
LBO
input.
In
the
case
of
input
I2
(Ay)
this
data
is
valid
for
two
cycles
because
ADV
is
high
and
has
suspended
the
burst.
3.
C
S
0timing
transitions
are
identical
but
inverted
to
the
CE
and
CS
1
signals.
For
example,
when
CE
and
CS
1are
LOW
on
this
waveform,
CS
0is
HIGH.
A
D
R
E
S
C
L
K
A
D
S
P
A
D
S
C
tC
Y
C
tS
S
tH
S
tC
H
tC
L
tH
A
tS
A
x
A
y
tH
W
B
W
x
A
D
V
D
A
T
A
O
U
T
O
E
tH
C
tS
D
S
in
g
le
W
ri
te
B
u
rs
t
W
ri
te
I1
(A
x
)
I2
(A
y
)
I2
(A
y
)
(A
D
V
s
u
s
p
e
n
d
s
b
u
rs
t)
I2
(A
z
)
tH
D
B
u
rs
t
R
e
a
d
E
x
te
n
d
e
d
B
u
rs
t
W
ri
te
tO
H
Z
D
A
T
A
IN
tS
A
V
tS
W
O
4
(A
w
)
C
E
,
C
S
1
tH
W
B
W
E
tS
W
(N
o
te
3
)
I1
(A
z
)
A
z
I4
(A
y)
I1
(A
y
)
I4
(A
y)
I3
(A
y
)
tS
C
B
W
E
is
ig
n
o
re
d
w
h
e
n
A
D
S
P
in
it
ia
te
s
a
c
y
c
le
a
n
d
is
s
a
m
p
le
d
o
n
e
x
t
c
lo
c
k
ri
s
in
g
e
d
g
e
B
W
x
is
ig
n
o
re
d
w
h
e
n
A
D
S
P
in
it
ia
te
s
a
c
y
c
le
a
n
d
is
s
a
m
p
le
d
o
n
e
x
t
c
lo
c
k
ri
s
in
g
e
d
g
e
I3
(A
z
)
O
3
(A
w
)
5
3
0
1
d
rw
1
,
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