參數(shù)資料
型號: 73K222AU-IH
廠商: TDK Corporation
英文描述: Single-Chip Modem Modem with UART
中文描述: 單芯片調(diào)制解調(diào)器調(diào)制解調(diào)器與異步
文件頁數(shù): 17/28頁
文件大?。?/td> 160K
代理商: 73K222AU-IH
73K222AL
V.22, V.21, Bell 212A, 103
Single-Chip Modem
17
ELECTRICAL SPECIFICATIONS
(continued)
DYNAMIC CHARACTERISTICS AND TIMING
(TA = -40
°
C to +85
°
C, VDD = recommended range unless otherwise noted.)
PARAMETER
CONDITION
MIN
NOM
MAX
UNIT
PSK Modulator
Carrier Suppression
Measured at TXA
55
dB
Output Amplitude
TX scrambled marks
-11.5
-10.0
-9
dBm0
FSK Mod/Demod
Output Frequency Error
CLK = 11.0592 MHz
-0.35
+0.35
%
Transmit Level
Transmit Dotting Pattern
-11.5
-10.0
-9
dBm0
Harmonic Distortion
in 700-2900 Hz band
THD in the alternate band
DPSK or FSK
-60
-50
dB
Output Bias Distortion
Transmit Dotting Pattern
in ALB @ RXD
±8
%
Total Output Jitter
Random Input in ALB @ RXD
-15
+15
%
DTMF Generator
Frequency Accuracy
-0.25
+0.25
%
Output Amplitude
Low Band, DPSK Mode
-10
-9
-8
dBm0
Output Amplitude
High Band, DPSK Mode
-8
-7
-6
dBm0
Twist
High-Band to Low-Band, DPSK Mode
1.0
2.0
3.0
dB
Long Loop Detect
DPSK or FSK
-38
-28
dBm0
Dynamic Range
Refer to Performance Curves
45
dB
Call Progress Detector
Detect Level
2-Tones in 350-600 Hz band
-34
0
dBm0
Reject Level
2-Tones in 350-600 Hz band
-41
dBm0
Delay Time
-70 dBm0 to -30 dBm0 STEP
27
80
ms
Hold Time
-30 dBm0 to -70 dBm0 STEP
27
80
ms
Hysteresis
NOTE: Parameters expressed in dBm0 refer to the following definition:
2
dB
0 dB loss in the Transmit path to the line.
2 dB gain in the Receive path from the line.
Refer to the Basic Box Modem diagram in the Applications section for the DAA design.
相關(guān)PDF資料
PDF描述
73K222AU-IP Single-Chip Modem Modem with UART
73K222BL V.22, V.21, Bell 212A,Bell 103 Single-Chip Modem with Integrated Hybrid(V.22, V.21, Bell 212A,Bell 103,帶混合電路的單片Modem)
73K224BL V.22bis/V.22/V.21/Bell 212A/103 Single-Chip Modem w/ Integrated Hybrid(V.22bis/V.22/V.21/Bell 212A/103單片Modem w/ 集成混合電路)
73K224L V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem
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