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參數(shù)資料
| 型號： | 73K224BL-IGT |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Single-Chip Modem w/ Integrated Hybrid |
| 中文描述： | 單芯片調(diào)制解調(diào)器瓦特/集成混合 |
| 文件頁數(shù)： | 5/33頁 |
| 文件大?。?/td> | 237K |
| 代理商： | 73K224BL-IGT |
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73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
5
PIN DESCRIPTION
POWER
NAME
GND
VDD
PIN
1
16
TYPE
I
I
DESCRIPTION
System ground
Power supply input, 5 V ±10% (73K224BL). Bypass with 0.1
and 22 μF capacitors to GND.
An internally generated reference voltage. Bypass with
0.1 μF capacitor to ground.
Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 M
resistor. ISET should be bypassed to GND with a
0.1 μF capacitor.
VREF
31
O
ISET
28
I
PARALLEL MICROPROCESSOR CONTROL INTERFACE MODE
ALE
13
I
ADDRESS LATCH ENABLE: The falling edge of ALE latches
the address on AD0-AD2 and the chip select on
CS
.
ADDRESS/DATA
BUS:
These
multiplexed lines carry information to and from the internal
registers.
CHIP SELECT: A low on this pin during the falling edge of
ALE allows a read cycle or a write cycle to occur. AD0-AD7
will not be driven and no registers will be written if
CS
(latched) is not active. The state of
CS
is latched on the
falling edge of ALE.
OUTPUT CLOCK: This pin is selectable under processor
control to be either the crystal frequency (for use as a
processor clock) or 16 times the data rate for use as a baud
rate clock in DPSK modes only. The pin defaults to the
crystal frequency on reset.
INTERRUPT: This open drain output signal is used to inform
the processor that a detect flag has occurred. The processor
must then read the Detect Register to determine which detect
triggered the interrupt.
INT
will stay low until the processor
reads the detect register or does a full reset.
READ: A low requests a read of the 73K224BL internal
registers. Data can not be output unless both
RD
and the
latched
CS
are active or low.
RESET: An active high signal on this pin will put the chip into
an inactive state. All Control Register bits (CR0, CR1, tone)
will be reset. The output of the CLK pin will be set to the
crystal frequency. An internal pull-down resistor permits
power-on-reset using a capacitor to VDD.
AD0-AD7
5-12
I/O
bi-directional
tri-state
CS
23
I
CLK
2
O
INT
20
O
RD
15
I
RESET
30
I
相關PDF資料 |
PDF描述 |
|---|---|
| 73K224BL-IH | Single-Chip Modem w/ Integrated Hybrid |
| 73K324BL | Single-Chip Modem w/Integrated Hybrid |
| 73K324BL-IGT | CONN, SHROUDED HDR, 34PIN, MALE, 0.100 |
| 73K324BL-IH | Four Wall Header; No. of Contacts:34; Pitch Spacing:0.1"; No. of Rows:2; Gender:Header; Body Material:Glass-filled Polyester; Contact Plating:Nickel; Leaded Process Compatible:No; Mounting Type:Through Hole RoHS Compliant: No |
| 73K324L | EMBASE |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73K224BL-IH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Modem w/ Integrated Hybrid |
| 73K224BL-IH/F | 功能描述:電信集成電路 Modem Data Pump With Hybrid Relay Driver RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| 73K224BL-IHR/F | 功能描述:電信集成電路 Modem Data Pump With Hybrid Relay Driver RoHS:否 制造商:STMicroelectronics 類型:Telecom IC - Various 工作電源電壓:4.75 V to 5.25 V 電源電流: 工作溫度范圍:- 40 C to + 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PQFP-100 封裝:Tray |
| 73K224L | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Single-Chip Modem |
| 73K224L-28IH | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem |
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