參數(shù)資料
型號(hào): 73K224BL-IH
廠(chǎng)商: Electronic Theatre Controls, Inc.
英文描述: Single-Chip Modem w/ Integrated Hybrid
中文描述: 單芯片調(diào)制解調(diào)器瓦特/集成混合
文件頁(yè)數(shù): 26/33頁(yè)
文件大?。?/td> 237K
代理商: 73K224BL-IH
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
26
DYNAMIC CHARACTERISTICS AND TIMING
(continued)
PARAMETER
TIMING
(Refer to Timing Diagrams)
TAL
TLA
CONDITION
*
MIN
NOM
MAX
UNIT
CS
/Address setup before ALE Low
CS
Address hold after ALE Low
ALE Low to
RD/WR
Low
RD/WR
Control to ALE High
Data out from
RD
Low
ALE width
Data float after
RD
High
RD
width
WR
width
Data setup before
WR
High
Data hold after
WR
High
Data out after EXCLK Low
WR
after EXCLK Low
Data setup before EXCLK Low
Address setup before control**
Address hold after control**
Data Hold after EXCLK
12
0
10
10
0
0
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS
AD0-AD7
TLC
TCL
TRD
TLL
TRDF
TRW
TWW
TDW
TWD
TCKD
TCKW (serial mode)
TDCK (serial mode)
TAC (serial mode)
TCA (serial mode)
TWH (serial mode)
70
50
50
150
15
12
200
150
150
50
50
50
* All timing parameters are targets and not guaranteed.
** Control for setup is the falling edge of
RD
or
WR
. Control for hold is the falling edge of
RD
or the rising
edge of
WR
.
NOTE: Asserting ALE,
CS
, and
RD
or
WR
concurrently can cause unintentional register accesses. When
using non-8031 compatible processors, care must be taken to prevent this from occurring when
designing the interface logic.
相關(guān)PDF資料
PDF描述
73K324BL Single-Chip Modem w/Integrated Hybrid
73K324BL-IGT CONN, SHROUDED HDR, 34PIN, MALE, 0.100
73K324BL-IH Four Wall Header; No. of Contacts:34; Pitch Spacing:0.1"; No. of Rows:2; Gender:Header; Body Material:Glass-filled Polyester; Contact Plating:Nickel; Leaded Process Compatible:No; Mounting Type:Through Hole RoHS Compliant: No
73K324L EMBASE
73K324L-28IH COSSE
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