參數(shù)資料
型號(hào)： 73M1903-EVM-ETSI
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 43/47頁(yè)
文件大?。?/td> 0K
描述： BOARD DEMO 73M1903 ETSI 203IMPED
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，模擬前端（AFE）
已用 IC / 零件： *
主要屬性： *
次要屬性： *
已供物品： *
DS_1903_032
73M1903 Data Sheet
Rev. 2.1
5
1.1
Serial Interface
The serial data port is a bi-directional port that is supported by many DSPs. Although the 73M1903 is a
peripheral to the DSP (host controller), the 73M1903 is the master of the serial port. It generates a serial
bit clock, Sclk, from a system clock, Sysclk, which is normally an output from an on-chip PLL that is
programmed by the user. The serial bit clock is derived by dividing the system clock by 18. The sclk rate,
Fsclk, is related to the frame synchronization rate, Fs, by the relationship Fsclk = 256 x Fs or Fs = Fsclk /
256 = Fsys / 18 / 256 = Fsys / 4608, where Fsys is the frequency of Sysclk. Fs is also the rate at which
both the transmit and receive data bytes are sent (received) to (by) the Host. Throughout this document
two pairs of sample rates, Fs, and crystal frequency, Fxtal, will be often cited to facilitate discussions.
They are:
1.
Fxtal1 = 27 MHz, Fs1 = 7.2 kHz
2.
Fxtal2 = 18.432 MHz, Fs2 = 8 kHz.
3.
Fxtal3 = 24.576 MHz, Fs3 = 9.6 kHz – chip default.
Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal
frequency, Fxtal, and therefore the serial bit clock will be Sclk = Fsys/18 = Fxtal/18.
Examples:
1. If Fxtal1 = 27.000 MHz, then sclk=1.500 MHz and Fs=sclk/256 = 5.859375 kHz.
2.
If Fxtal2 = 18.432 MHz, then sclk=1.024 MHz and Fs=sclk/256 = 4.00 kHz.
3.
If Fxtal3 = 24.576 MHz, then sclk=1.3653 MHz and Fs=sclk/256 = 5.33 kHz.
When 73M1903 is programmed through the serial port to a desired Fs and the PLL has settled out, the
system clock will transition to the PLL-based clock in a glitch-less manner.
Examples:
1.
If Fs1 = 7.2 kHz, Fsys = 4608 * Fs = 33.1776 MHz and sclk = Fsys / 18 = 1.8432 MHz.
2.
If Fs2 = 8.0 kHz, Fsys = 4608 * Fs = 36.8640 MHz and sclk = Fsys / 18 = 2.048 MHz.
3.
If Fs3 = 9.6 kHz, Fsys = 4608 * Fs = 44.2368 MHz and sclk = Fsys / 18 = 2.4576 MHz.
This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front
end, the chip will automatically run off the crystal until the host forces the transition by setting a bit in a
designated serial port register – location bit 7, 0Eh. The transition is forced on or after the second Frame
Synch period following the write to a designated PLL programming register (0Dh).
When reprogramming the PLL the host should first transition the system clock to the crystal before
reprogramming the PLL so that any transients associated with it will not adversely impact the serial port
communication.
Power saving is accomplished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h),
ENFE=0.
During the normal operation, a data
FS is generated by the 73M1903 at the rate of Fs. For every data FS
there are 16 bits transmitted and 16 bits received. The frame synchronization (
FS) signal is pin
programmable for type.
FS can either be early or late determined by the state of the TYPE input pin.
When the TYPE pin is left open, an early
FS is generated in the bit clock prior to the first data bit
transmitted or received. When held low, a late FS operates as a chip select; the
FS signal is active for all
bits that are transmitted or received. The TYPE input pin is sampled when the reset pin is active (low)
and ignored at all other times. The final state of the TYPE pin as the reset pin is de-asserted determines
the frame synchronization mode used.
相關(guān)PDF資料
PDF描述
M3UFK-1618J IDC CABLE - MKS16K/MC16G/MCF16K
GBM22DTKT CONN EDGECARD 44POS DIP .156 SLD
VI-JW2-EZ-F2 CONVERTER MOD DC/DC 15V 25W
CM453232-6R8JL INDUCTOR 6.8UH 285MA SMD
M3UGK-1618J IDC CABLE - MKS16K/MC16G/MCS16K
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
73M1903-EVM-WW 功能描述:BOARD DEMO 73M1903 PPU WORLDWIDE RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板
73M1903-IM/F 功能描述:電信線路管理 IC Modem AFE V.22Bis-V.92 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
73M1903-IM/F1 功能描述:電信線路管理 IC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
73M1903-IMR/F 功能描述:電信線路管理 IC Modem AFE V.22Bis-V.92 RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
73M1903-IMR/F1 功能描述:電信線路管理 IC RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類(lèi)型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*