參數(shù)資料
型號(hào)： 73M1903-IGV/F
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP32
封裝： LEAD FREE, TQFP-32
文件頁(yè)數(shù)： 42/45頁(yè)
文件大?。?/td> 449K
代理商： 73M1903-IGV/F
73M1903
Modem Analog Front End
DATA SHEET
ge: 6 of 45
2005 TERIDIAN Semiconductor Corporation
Rev 1.4
SERIAL INTERFACE
The serial data port is a bi-directional port that can be supported by most DSPs. Although the 73M1903
is a peripheral to the DSP (host controller), the 73M1903 is the master of the serial port. It generates a
serial bit clock, Sclk, from a system clock, Sysclk, which is normally an output from an on-chip PLL that
can be programmed by the user. The serial bit clock is always derived by dividing the system clock by 18.
The sclk rate, Fsclk, is related to the frame synchronization rate, Fs, by the relationship Fsclk = 256 x Fs
or Fs = Fsclk / 256 = Fsys / 18 / 256 = Fsys / 4608, where Fsys is the frequency of Sysclk. Fs is also the
rate at which both the transmit and receive data bytes are sent (received) to (by) the Host. Throughout
this document two pairs of sample rate, Fs, and crystal frequency, Fxtal, will be often cited to facilitate
discussions. They are:
1. Fxtal1 = 27MHz, Fs1 = 7.2kHz
2. Fxtal2 = 18.432MHz, Fs2 = 8kHz.
3. Fxtal3 = 24.576MHz, Fs3 = 9.6kHz – chip default.
Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal
frequency, Fxtal, and therefore the serial bit clock will be sclk = Fsys/18 = Fxtal/18.
Examples:
1. If Fxtal1 = 27.000MHz, then sclk=1.500MHz and Fs=sclk/256 = 5.859375kHz.
2. If Fxtal2 = 18.432MHz, then sclk=1.024MHz and Fs=sclk/256 = 4.00kHz.
3. If Fxtal3 = 24.576MHz, then sclk=1.3653MHz and Fs=sclk/256 = 5.33kHz.
When 73M1903 is programmed through the serial port to a desired Fs and the PLL has settled out, the
system clock will transition to the PLL-based clock in a glitch-less manner.
Examples:
1. If Fs1 = 7.2kHz, Fsys = 4608 * Fs = 33.1776MHz and sclk = Fsys / 18 = 1.8432MHz.
2. If Fs2 = 8.0kHz, Fsys = 4608 * Fs = 36.8640MHz and sclk = Fsys / 18 = 2.048MHz.
3. If Fs3 = 9.6kHz, Fsys = 4608 * Fs = 44.2368MHz and sclk = Fsys / 18 = 2.4576MHz.
This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front
end, the chip will automatically run off the crystal until the host forces the transition by setting a bit in a
designated serial port register – location bit 7, 0Eh. The transition should be forced on or after the
second Frame Synch period following the write to a designated PLL programming register (0Dh).
When reprogramming the PLL the host should first transition the system clock to the crystal before
reprogramming the PLL so that any transients associated with it will not adversely impact the serial port
communication.
Power saving is accomplished by disabling the analog front end by clearing bit 7 of CTRL1 (address 00h),
ENFE=0.
During the normal operation, a data
FS is generated by the 1903 at the rate of Fs. For every data FSB
there are 16 bits transmitted and 16 bits received. The frame synchronization (
FS) signal is pin
programmable for type.
FS can either be early or late determined by the state of the TYPE input pin.
When Type pin is left open, an early
FS is generated in the bit clock prior to the first data bit transmitted
相關(guān)PDF資料
PDF描述
73M1903-IGV SPECIALTY CONSUMER CIRCUIT, PQFP32
73M1903-IM SPECIALTY CONSUMER CIRCUIT, QCC32
73M1903-IM/F SPECIALTY CONSUMER CIRCUIT, PQCC32
73M1903-IMR/F SPECIALTY CONSUMER CIRCUIT, PQCC32
73M1903-IVT/F SPECIALTY CONSUMER CIRCUIT, PDSO20
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