參數(shù)資料
型號: 73M1903C-IM/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PQCC32
封裝: LEAD FREE, QFN-32
文件頁數(shù): 34/48頁
文件大?。?/td> 487K
代理商: 73M1903C-IM/F
73M1903C Data Sheet
DS_1903C_033
4
Rev. 5.0
1
Pin Description
The 73M1903C modem Analog Front End (AFE) IC is available in a 32-pin QFN package.
Table 1 describes the function of each pin. There are three pairs of power supply pins, VPA (analog),
VPD (digital) and VPPLL (PLL). They should be separately decoupled from the supply source in order to
isolate digital noise from the analog circuits internal to the chip. VPPLL can be directly connected to
VPD. Failure to adequately isolate and decouple these supplies will compromise device performance.
Table 1: 32 QFN Pin Description
Pin Nam e
Type
Pin #
Description
VND
GND
1, 22
Negative Digital Ground.
VNA
GND
16
Negative Analog Ground.
VPD
PWR
2, 25
Positive Digital Supply.
VPA
PWR
9
Positive Analog Supply.
VPPLL
PWR
20
Positive PLL Supply, shared with VPD.
VNPLL
PWR
17
Negative PLL Ground.
RST
I
26
Master reset. When this pin is a logic 0 all registers are
reset to their default states; Weak-pulled high-default. A
low pulse longer than 100 ns is needed to reset the
device. The device will be ready within 100 s after this
pin goes to logic 1 state.
OSCIN
I
19
Crystal oscillator input. When providing an external clock
source, drive OSCIN.
OSCOUT
O
18
Crystal oscillator circuit output pin.
GPIO(0-7)
I/O
3, 4, 5, 6, 23
24, 30, 31
Software definable digital input/output pins.
6
7
8
9
5
4
3
2
1
17
18
19
20
24
23
22
21
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
VND
VPD
GPIO0
GPIO1
GPIO2
GPIO3
SCLK
GPIO5
GPIO4
VND
FSD
VPPLL
OSCIN
OSCOUT
VNPLL
VPA
T
X
AN2
T
XA
P1
T
XA
P2
RX
AN
RX
AP
V
NA
TERIDIAN
73M1903C
VPD
S
DO
UT
GP
IO7
GP
IO6
S
DI
N
S
ckM
o
d
e
T
YPE
RS
T
73M1903C QFN 32
FS
T
X
AN1
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