參數(shù)資料
型號: 73M1903C-IM
廠商: TERIDIAN SEMICONDUCTOR CORP
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, QCC32
封裝: LEAD FREE, QFN-32
文件頁數(shù): 6/45頁
文件大小: 459K
代理商: 73M1903C-IM
73M1903C
Modem Analog Front End
DATA SHEET
Page: 14 of 45
2005 TERIDIAN Semiconductor Corporation
Rev 3.4
Control Register (CTRL 11): Address 0Bh
Reset State 12h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Ndvsr6
Ndvsr5
Ndvsr4
Ndvsr3
Ndvsr2
Ndvsr1
Ndvsr0
Ndvsr[6:0] represents the divisor. If Nrst{2:0] =0 this register is ignored.
Control Register (CTRL 12): Address 0Ch
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Nseq7
Nseq6
Nseq5
Nseq4
Nseq3
Nseq2
Nseq1
Nseq0
Nseq[7:0] represents the divisor sequence.
Control Register (CTRL 13): Address 0Dh
Reset State 48h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Xtal1
Xtal0
reserved
ThLk0
unused
Nrst2
Nrst1
Nrst0
Xtal[1:0] :
00 = Xtal osc. bias current at 120A
01 = Xtal osc. bias current at 180A
10 = Xtal osc. bias current at 270A
11 = Xtal osc. bias current at 450A
ThLk0 : Threshold setting for the PLL Lock condition. 1 = PLL locks 80% of “1” of raw data 0 = 90%.
If OSCIN is used as a Clock input, “00” setting should be used to save power(=167A at 27.648MHz).
Nrst[3:0] represents the rate at which the NCO sequence register is reset.
The address ODh must be the last register to be written to when effecting a change in PLL.
Control Register (CTRL 14): Address 0Eh
Reset State 00h
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Frcvco
PwdnPLL Lokdet
unused
Frcvco = 1 forces VCO as system clock. This is reset upon RST, PwdnPLL = 1 or Enfe = 0. Both
PwdnPLL and Enfe are delayed coming out of digital section to keep PLL alive long enough to transition
the system clock to crystal clock when Frcvco is reset by PwdnPLL or Enfe.
PwdnPll = 1 forces Power down of PLL analog section.
Lokdet: Read only. 1 = PLL locked, 0 = PLL not locked.
Addr. 00h bit 7
Enfe
Addr. 0Eh bit 6
PwdnPLL
PLL
0
X
PLL Power Off
1
0
PLL Power On
1
PLL Power Off
Table 5: PLL Power Down
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