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參數資料
| 型號： | 73M1903C-IMR/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數： | 45/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MODEM AFE MULTIREGIONAL 32QFN |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 通道數： | 2 |
| 電壓 - 電源，模擬： | 3 V ~ 3.6 V |
| 電壓 - 電源，數字： | 3 V ~ 3.6 V |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 32-QFN（5x5） |
| 包裝： | 帶卷 (TR) |
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73M1903C Data Sheet
DS_1903C_033
6
Rev. 5.0
2
Modem Analog Front End (MAFE) Serial Interface
The Modem Analog Front End (MAFE) serial data port is a bi-directional port that is supported by most
DSPs. The typical I
2S (Inter-IC Sound, NXP semiconductor) bus can be easily converted into MAFE
compatible interface. The 73M1903C can be configured either as a master or a slave of the serial
interface. When the 73M1903C is configured as a master device, it generates a serial bit clock, Sclk,
from a system clock, Sysclk, which is normally an output from an on-chip PLL that can be programmed by
the user. In master mode, the serial bit clock is always derived by dividing the system clock by 18. The
Sclk rate, Fsclk, is related to the frame synchronization rate (sample rate), Fs, by the relationship Fsclk =
256 x Fs or Fs = Fsclk / 256 = Fsys / 18 / 256 = Fsys / 4608, where Fsys is the frequency of Sysclk. Fs is
also the rate at which both transmit and receive data bytes are sent (received) to (by) the Host.
Throughout this document two pairs of sample rate, Fs, and crystal frequency, Fxtal, will be often cited to
facilitate discussions. They are:
1.
Fxtal1 = 27 MHz, Fs1 = 7.2 kHz
2.
Fxtal2 = 18.432 MHz, Fs2 = 8 kHz.
3.
Fxtal3 = 24.576 MHz, Fs3 = 9.6 kHz
Upon reset, until a switch to the PLL based clock, Pllclk, occurs, the system clock will be at the crystal
frequency, Fxtal, and therefore the serial bit clock will be sclk = Fsys/18 = Fxtal/18.
Examples:
1. If Fxtal1 = 27.000 MHz, then sclk=1.500 MHz and Fs=sclk/256 = 5.859375 kHz.
2.
If Fxtal2 = 18.432 MHz, then sclk=1.024 MHz and Fs=sclk/256 = 4.00 kHz.
3.
If Fxtal3 = 24.576 MHz, then sclk=1.3653 MHz and Fs=sclk/256 = 5.33 kHz.
When 73M1903C is programmed through the serial port to a desired Fs and the PLL has settled out, the
system clock will transition to the PLL-based clock in a glitch-less manner.
Examples:
1. If Fs1 = 7.2 kHz, Fsys = 4608 * Fs = 33.1776 MHz and sclk = Fsys / 18 = 1.8432 MHz.
2.
If Fs2 = 8.0 kHz, Fsys = 4608 * Fs = 36.8640 MHz and sclk = Fsys / 18 = 2.048 MHz.
3. If Fs3 = 9.6 kHz, Fsys = 4608 * Fs = 44.2368 MHz and sclk = Fsys / 18 = 2.4576 MHz.
This transition is entirely controlled by the host. Upon reset or power down of PLL and/or analog front
end, the chip will automatically run off the crystal until the host forces the transition by setting Frcvco bit
(Bit 7 in Register0E). The transition should be forced on or after the second frame synch period following
the write to a designated PLL programming registers (Register08 to Register0D).
When reprogramming the PLL the host should first transition the system clock to the crystal before
reprogramming the PLL so that any transients associated with it will not adversely impact the serial port
communication.
Power saving is accomplished by disabling the analog front end by clearing ENFE bit (bit 7 Register00).
During the normal operation, a data frame sync signal (
FS) is generated by the 73M1903C at the rate of
Fs. For every data
FS there are 16 bits transmitted and 16 bits received.
The frame synchronization (
FS) signal is pin programmable for type (Figure 1). FS can either be early or
late determined by the state of the TYPE input pin. When Type pin is left open (high), an early
FS is
generated in the bit clock prior to the first data bit transmitted or received. When held low, a late
FS
operates as a chip select; the
FS signal is active (low) for all bits that are transmitted or received. The
TYPE input pin is sampled when the reset pin is active (low) and ignored at all other times. The final
state of the TYPE pin as the reset pin is de-asserted determines the frame synchronization mode used.
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參數描述 |
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| 73M1903-EVM-600 | 功能描述:網絡開發(fā)工具 73M1903 w/Ppu & 600 Ohm Term-Usa & Japan RoHS:否 制造商:Rabbit Semiconductor 產品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數據速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| 73M1903-EVM-ETSI | 功能描述:網絡開發(fā)工具 73M1903 w/Etsi 203 Complex Imped. Term RoHS:否 制造商:Rabbit Semiconductor 產品:Development Kits 類型:Ethernet to Wi-Fi Bridges 工具用于評估:RCM6600W 數據速率:20 Mbps, 40 Mbps 接口類型:802.11 b/g, Ethernet 工作電源電壓:3.3 V |
| 73M1903-EVM-WW | 功能描述:BOARD DEMO 73M1903 PPU WORLDWIDE RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 產品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| 73M1903-IM/F | 功能描述:電信線路管理 IC Modem AFE V.22Bis-V.92 RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| 73M1903-IM/F1 | 功能描述:電信線路管理 IC RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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