參數(shù)資料
型號: 73S1210F-68IM/F/P
廠商: Maxim Integrated Products
文件頁數(shù): 52/126頁
文件大?。?/td> 0K
描述: IC SMART CARD READER PROG 68-QFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 260
系列: 73S12xx
核心處理器: 80515
芯體尺寸: 8-位
速度: 24MHz
連通性: I²C,智能卡,UART/USART
外圍設備: LED,POR,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-VFQFN 裸露焊盤
包裝: 管件
DS_1210F_001
73S1210F Data Sheet
Rev. 1.4
31
Miscellaneous Control Register 1 (MISCtl1): 0xFFF2
0x10
Table 16: The MISCtl1 Register
MSB
LSB
FRPEN
FLSH66
Bit
Symbol
Function
MISCtl1.7
MISCtl1.6
MISCtl1.5
FRPEN
Flash Read Pulse enable (low). If FRPEN = 1, the Flash Read signal is
passed through with no change. When FRPEN = 0 a one-shot circuit that
shortens the Flash Read signal is enabled to save power. The Flash Read
pulse will shorten to 40 or 66ns (approximate based on the setting of the
FLSH66 bit) in duration, regardless of the MPU clock rate. For MPU clock
frequencies greater than 10MHz, this bit should be set high.
MISCtl1.4
FLSH66
When high, creates a 66ns Flash read pulse, otherwise creates a 40ns
read pulse when FRPEN is set.
MISCtl1.3
MISCtl1.2
MISCtl1.1
MISCtl1.0
Master Clock Control Register (MCLKCtl): 0x8F
0x0A
Table 17: The MCLKCtl Register
MSB
LSB
HSOEN
KBEN
SCEN
MCT.2
MCT.1
MCT.0
Bit
Symbol
Function
MCLKCtl.7
HSOEN*
High-speed oscillator enable. When set = 1, disables the high-speed
crystal oscillator and VCO/PLL system. This bit is not changed when the
PWRDN bit is set but the oscillator/VCO/PLL is disabled.
MCLKCtl.6
KBEN
1 = Disable the keypad logic clock. This bit is not changed in PWRDN
mode but the function is disabled.
MCLKCtl.5
SCEN
1 = Disable the smart card logic clock. This bit is not changed in PWRDN
mode but the function is disabled. Interrupt logic for card insertion/removal
remains operable even with smart card clock disabled.
MCLKCtl.4
MCLKCtl.3
MCLKCtl.2
MCT.2
This value determines the ratio of the VCO frequency (MCLK) to the
high-speed crystal oscillator frequency such that:
MCLK = (MCount*2 + 4)*Fxtal. The default value is MCount = 2h such
that MCLK = (2*2 + 4)*12.00MHz = 96MHz.
MCLKCtl.1
MCT.1
MCLKCtl.0
MCT.0
*Note: The HSOEN bit should never be set under normal circumstances. Power down control should
only be initiated via use of the PWRDN bit in MISCtl0.
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