參數(shù)資料
型號: 73S1210F-68IMR/F/P
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC68
封裝: LEAD FREE, QFN-68
文件頁數(shù): 43/126頁
文件大?。?/td> 1231K
代理商: 73S1210F-68IMR/F/P
DS_1210F_001
73S1210F Data Sheet
Rev. 1.4
23
The master clock control register enables different sections of the clock circuitry and specifies the value
of the VCO Mcount divider. The MCLK must be configured to operate at 96MHz to ensure proper
operation of some of the peripheral blocks according to the following formula:
MCLK = (Mcount * 2 + 4) * FXTAL = 96MHz
Mcount is configured in the MCLKCtl register must be bound between a value of 1 to 10. The possible
crystal or external clock frequencies for getting MCLK = 96MHz are shown in Table 11.
Table 11: Frequencies and Mcount Values for MCLK = 96MHz
FXTAL (MHz)
Mcount (N)
12.00
2
9.60
3
8.00
4
6.86
5
6.00
6
Master Clock Control Register (MCLKCtl): 0x8F
0x0A
The MPU clock that drives the CPU core defaults to 3.6923MHz after reset. The MPU clock is scalable
by configuring the MPU Clock Control register.
Table 12: The MCLKCtl Register
MSB
LSB
HSOEN
KBEN
SCEN
MCT.2
MCT.1
MCT.0
Bit
Symbol
Function
MCLKCtl.7
HSOEN
High-speed oscillator disable. When set = 1, disables the high-speed
crystal oscillator and VCO/PLL system. Do not set this bit = 1.
MCLKCtl.6
KBEN
1 = Disable the keypad logic clock.
MCLKCtl.5
SCEN
1 = Disable the smart card logic clock.
MCLKCtl.4
MCLKCtl.3
MCLKCtl.2
MCT.2
This value determines the ratio of the VCO frequency (MCLK) to the
high-speed crystal oscillator frequency such that:
MCLK = (MCount*2 + 4)* FXTAL. The default value is MCount = 2h such
that MCLK = (2*2 + 4)*12.00MHz = 96MHz.
MCLKCtl.1
MCT.1
MCLKCtl.0
MCT.0
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