The 73S1210F contains a circuit to detect a low-voltag" />
參數(shù)資料
型號: 73S1210F-68IMR/F
廠商: Maxim Integrated Products
文件頁數(shù): 6/126頁
文件大?。?/td> 0K
描述: IC SMART CARD READER 68-QFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
系列: 73S12xx
核心處理器: 80515
芯體尺寸: 8-位
速度: 24MHz
連通性: I²C,智能卡,UART/USART
外圍設(shè)備: LED,POR,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
DS_1210F_001
73S1210F Data Sheet
Rev. 1.4
103
1.7.16 VDD Fault Detect Function
The 73S1210F contains a circuit to detect a low-voltage condition on the supply voltage VDD. If enabled,
it will deactivate the active internal smart card interface when VDD falls below the VDD Fault threshold. The
register configures the VDD Fault threshold for the nominal default of 2.3V* or a user selectable threshold.
The user’s code may load a different value using the FOVRVDDF bit = 1 after the power-up cycle has
completed.
VDDFault Control Register (VDDFCtl): 0xFFD4
0x00
Table 108: The VDDFCtl Register
MSB
LSB
FOVRVDDF VDDFLTEN
STXDAT.3
VDDFTH.2
VDDFTH.1
VDDFTH.0
Bit
Symbol
Function
VDDFCtl.7
VDDFCtl.6
FOVRVDDF
Setting this bit high will allow the VDDFLT(2:0) bits set in this register to control
the VDDFault threshold. When this bit is set low, the VDDFault threshold will
be set to the factory default setting of 2.3V*.
VDDFCtl.5
VDDFLTEN
Set = 1 will disable VDD Fault operation.
VDDFCtl.4
VDDFCtl.3
VDDFCtl.2
VDDFTH.2
VDD Fault Threshold.
Bit Value(2:0)
VDDFault Voltage
000
2.3 (nominal default)
001
2.4
010
2.5
011
2.6
100
2.7
101
2.8
110
2.9
111
3.0
VDDFCtl.1
VDDFTH.1
VDDFCtl.0
VDDFTH.0
* Note: The VDD Fault factory default can be set to any threshold as defined by bits VDDFTH(2:0). The
73S1210F has the capability to burn fuses at the factory to set the factory default to any of these
voltages. Contact Teridian for further details.
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