參數(shù)資料
型號: 73S1215F-44IMR/F
廠商: Maxim Integrated Products
文件頁數(shù): 81/136頁
文件大?。?/td> 0K
描述: IC SMART CARD READER 44-QFN
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 2,500
系列: 73S12xx
核心處理器: 80515
芯體尺寸: 8-位
速度: 24MHz
連通性: I²C,智能卡,UART/USART,USB
外圍設備: LED,POR,WDT
輸入/輸出數(shù): 9
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: 閃存
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
DS_1215F_003
73S1215F Data Sheet
Rev. 1.4
49
Interrupt Priority 0 Register (IP0): 0xA9
0x00
Table 46: The IP0 Register
MSB
LSB
WDTS
IP0.5
IP0.4
IP0.3
IP0.2
IP0.1
IP0.0
Bit
Symbol
Function
IP0.6
WDTS
Watchdog timer status flag. Set when the watchdog timer has expired.
The internal reset will be generated, but this bit will not be cleared by the
reset. This allows the user program to determine if the watchdog timer
caused the reset to occur and respond accordingly. Can be read and
cleared by software.
Note: The remaining bits in the IP0 register are not used for watchdog control.
Watchdog Timer Reload Register (WDTREL): 0x86
0x00
Table 47: The WDTREL Register
MSB
LSB
WDPSEL WDREL6 WDREL5 WDREL4 WDREL3 WDREL2 WDREL1 WDREL0
Bit
Symbol
Function
WDTREL.7
WDPSEL
Prescaler select bit. When set, the watchdog is clocked through an
additional divide-by-16 prescaler.
WDTREL.6
to
WDTREL.0
WDREL6-0
Seven bit reload value for the high-byte of the watchdog timer. This
value is loaded to the WDT when a refresh is triggered by a
consecutive setting of bits WDT and SWDT.
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