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| 型號： | 73S1217F-68IMR/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 80/93頁 |
| 文件大小： | 0K |
| 描述： | IC SMART CARD READER 68-QFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 系列： | 73S12xx |
| 核心處理器： | 80515 |
| 芯體尺寸： | 8-位 |
| 速度： | 24MHz |
| 連通性： | I²C，智能卡，UART/USART，USB |
| 外圍設(shè)備： | LED，POR，WDT |
| 輸入/輸出數(shù)： | 8 |
| 程序存儲器容量： | 64KB（64K x 8） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.7 V ~ 6.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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UG_12xxF_016
73S12xxF Software User Guide
Rev. 1.50
81
punIccTSTimeOut: Input/output parameter
Specifies the maximum delay in clock cycles between the de-assertion of the RST
signal and the leading edge of the TS character of the ATR. [Default value is 40 000]
pucIccRxErrorCounterT0: Input/output parameter
Specifies the maximum number of errors allowed when the Interface Device is in
reception mode in T=0 protocol.
pucIccTxErrorCounterT0: Input/output parameter
Specifies the maximum number of errors when the Interface Device is in
transmission mode in T=0 protocol.
pucIccTxErrorCounterT1: Input/output parameter
Specifies the maximum number of errors when T=1. The most significant nibble
gives the maximum number of R(NA) block transmissions, while the least significant
nibble gives the maximum number of I or S-block retransmissions.
ucIccConfigurationByte: Input/output parameter
This byte contains the following configuration bits:
[b0]
bIccIFSDRequestT1: Input/output. Specifies if the next I-Block will be
preceded by an S(IFS request) (TRUE) or not (FALSE).
[b1]
bIccDeactivatedOnTimeOutErrorT1: Input/output. Specifies if the Smart Card
interface is to be de-activated (TRUE) on a TimeOut error. Otherwise, an error
recovery procedure is engaged.
[b2]
bIccNADErrorCheckingT1: Input/output. Specifies whether the NAD errors
are to be checked (TRUE) or not (FALSE).
[b3]
bIccABORTManagementT1: Input/output. Specifies whether the ABORT
Request is to be managed (TRUE) or if the contacts are to be de-activated on
S(ABORT Request) reception (FALSE).
[b4]
bIccRESYNCHManagementT1: Input/output. Specifies whether an
S(RESYNCH Request) command is to be sent when too many errors occur
(TRUE) or if a de-activation sequence is to be initiated (FALSE).
[b5]
bIccRetransmitLastBlockAfterRESYNCHT1: Input/output. Specifies whether
the last block in T=1 protocol is to be retransmitted after a resynchronization
occurs or the whole command. [Useful for Microsoft IFDTESTs suite]
[b6]
bIccWarningStatusBytesManagementT0: Input/output. Specifies if the IFD
must inform the application level of whether the status bytes have been
received just after the command header transmission or after the command
data transmission (in T=0 protocol). [Useful for EMV Test suites]
[b7]
bIccDeactivateOnIFSDNegotiationError: Input/output. Specifies if the Smart
Card interface is to be de-activated on an IFSD negotiation error.
Icc_Hz: Input parameter
Specifies the desired Smart Card clock frequency. Available values are defined in
the API_Struct_12.h file (LAPI). The default value for both the internal and external
slots is 3.69 MHz.
Care must be taken to make sure the Smart Card Clock is slower than the CPU clock. Since the
CPU has much more overhead to process, a faster Smart Card clock may out run the CPU
resulting in unexpected or undesirable delays.
Since the Smart Card Clock for the external slots (slot ICC_2
ND or higher) is driven by the 73S12xxF
single source, all external slots will share the same SC clock configuration. For example, if an application
sets the first external slot to one rate, subsequent calls to this function with a different rate will be ignored.
DebouncePUEnable: Input parameter
The higher order (most significant) nibble of this byte enables (SC_DEBOUNCEON)
or disables (SC_DEBOUNCEOFF) card debounce. The low order (least significant)
nibble of this byte enables (TRUE) or disables (FALSE) the Pull-Up.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73S1217F-68M/F/PB | 制造商:Maxim Integrated Products 功能描述:OLD P/N 73S1217F-68IM/F/P = NEW P/N 73S1217F-68M/F/PB PIN PD - Rail/Tube |
| 73S1217F-68M/F/PE | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| 73S1217F-68MR/F/PE | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| 73S1217F-EB | 功能描述:開發(fā)板和工具包 - 8051 73S1217F Eval Brd (Usb Cable, Doc. Cd) RoHS:否 制造商:Silicon Labs 產(chǎn)品:Development Kits 工具用于評估:C8051F960, Si7005 核心: 接口類型:USB 工作電源電壓: |
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