參數(shù)資料
型號: 73S8009C-20IM/F
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, QCC20
封裝: ROHS COMPLIANT, QFN-20
文件頁數(shù): 6/33頁
文件大?。?/td> 481K
代理商: 73S8009C-20IM/F
73S8009C Data Sheet
DS_8009C_025
14
Rev. 1.3
Symbol
Parameter
Condition
Min
Nom
Max
Unit
Reset and Clock for card interface, RST, CLK
VOH
Output level, high
IOH =-200A
0.9 * VCC
VCC
V
VOL
Output level, low
IOL=200A
0
0.15
*VCC
V
VINACT
Output voltage when
outside of session
IOL = 0
0.1
V
IRST_LIM
Output current limit, RST
30
mA
ICLK_LIM
Output current limit, CLK
70
mA
tR, tF
Output rise time, fall time
CL = 35pF for CLK, 10% to
90%
12
ns
CL = 200pF for RST, 10% to
90%
100
ns
δ
Duty cycle for CLK
CL =35pF, FCLK 20MHz,
CLKIN duty cycle is 48% to
52%.
45
55
%
2.4
Digital Signals Characteristics
Table 5 lists the 73S8009C digital signals characteristics.
Table 5: Digital Signals Characteristics
Symbol
Parameter
Condition
Min
Nom
Max
Unit
Digital I/O
(except for I/OUC, AUX1UC, AUX2UC; see Smart Card Interface Requirements for those specifications)
VIL
Input Low Voltage
-0.3
0.8
V
VILOFFACK
Input low voltage for
OFF_ACK pin
OFF_REQ pin = VDD
-0.3
0.7
V
VIH
Input High Voltage
1.8
VDD + 0.3
V
VOL
Output Low Voltage
IOL = 2mA
0.45
V
VOH
Output High Voltage
IOH = -1mA
VDD - 0.45
V
ROUT
Pull-up resistor;
OFF, RDY
14
20
26
k
RACK
Resistor between
OFF_REQ and 0FF_ACK
70
100
130
k
|IIL1|
Input Leakage Current
GND < VIN < VDD
5
μA
tSL
Time from CS goes high to
interface active
50
ns
tDZ
Time from CS goes low to
interface inactive, Hi-Z
50
ns
tIS
Set-up time, control
signals to CS rising edge
50
ns
tSI
Hold time, control signals
from CS rising edge
50
ns
tID
Set-up time, control
signals to CS fall
50
ns
tDI
Hold time, control signals
from CS fall
50
ns
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