參數(shù)資料
型號: 73S8009R-IMR
廠商: TERIDIAN SEMICONDUCTOR CORP
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC20
封裝: 4 X 4 MM, 0.80 MM HEIGHT, QFN-20
文件頁數(shù): 2/23頁
文件大?。?/td> 342K
代理商: 73S8009R-IMR
73S8009R Data Sheet
DS_8009R_056
10
Rev. 1.3
Symbol
Parameter
Condition
Min
Nom
Max
Unit
Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC,
AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, AUX2UC.
VOH
Output level, high (I/O,
AUX1, AUX2)
IOH = 0 A
0.9 * VCC
VCC+0.1
V
IOH = -40 A
0.75 * VCC
VCC+0.1
VOH
Output level, high (I/OUC,
AUX1UC, AUX2UC)
IOH = 0 A
0.9 * VDD
VDD+0.1
V
IOH = -40 A
0.75 * VDD
VDD+0.1
VOL
Output level, low (I/O,
AUX1, AUX2)
IOL = 1 mA
0.15 * VCC
V
VOL
Output level, low (I/OUC,
AUX1UC, AUX2UC)
IOL = 1 mA
0.3
V
VIH
Input level, high (I/O,
AUX1, AUX2)
0.6 * VCC
VCC+0.30
V
VIH
Input level, high (I/OUC,
AUX1UC, AUX2UC)
1.8
VDD+0.30
V
VIL
Input level, low (I/O,
AUX1, AUX2)
-0.15
0.2 * VCC
V
VIL
Input level, low (I/OUC,
AUX1UC, AUX2UC)
-0.3
0.8
V
VINACT
Output voltage when
outside of session
IOL = 0
0.1
V
IOL = 1 mA
0.3
ILEAK
Input leakage
VIH = VCC
10
A
IIL
Input current, low (I/O,
AUX1, AUX2)
VIL = 0
0.65
mA
IIL
Input current, low (I/OUC,
AUX1UC, AUX2UC)
VIL = 0
0.7
mA
ISHORTL
Short circuit output
current
For output low, shorted to
VCC through 33
15
mA
ISHORTH
Short circuit output
current
For output high, shorted to
ground through 33
15
mA
tR, tF
Output rise time, fall time For I/O, AUX1, AUX2,
CL = 80 pF, 10% to 90%.
For I/OUC, AUX1UC,
AUX2UC, CL=50 pF, 10%
to 90%.
100
ns
tIR, tIF
Input rise, fall times
1
s
RPU
Internal pull-up resistor
Output stable for >200 ns
8
11
14
k
FDMAX
Maximum data rate
1
MHz
TFDIO
Delay, I/O to I/OUC, AUX1
to AUX1UC, AUX2 to
AUX2UC, I/OUC to I/O,
AUX1UC to AUX1,
AUX2UC to AUX2
(respectively falling edge
to falling edge and rising
edge to rising edge)
Edge from master to slave
measured at 50% point
60
100
200
ns
TRDIO
25
90
CIN
Input capacitance
10
pF
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