73S8010C
Smart Card Interface
DATA SHEET
Page: 9 of 27
2005 TERIDIAN Semiconductor Corporation
Rev 1.2
VOLTAGE SUPERVISON
Two voltage supervisors constantly check the level of the voltages VDD and VCC. A card deactivation sequence is
forced upon a fault of any of these voltage supervisors.
Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to
interface with the system controller. The VDD Voltage supervisor is also used to initialize the ISO-7816-3
sequencer at power-on, and also to deactivate the card at power-off or upon fault. The voltage threshold of the
VDD voltage supervisor is internally set by default to 2.3V nominal. However, it may be desirable, in some
applications, to modify this threshold value. The pin VDDF_ADJ (pin 18 in the SO package, pin 17 in the QFN
package) is used to connect an external resistor REXT1 to ground to raise the VDD fault voltage to another value,
VDDF (refer to the applications schematic diagram below). The resistor value is defined as follows:
REXT= 180k /(VDDF - 2.33)
An alternative method (more accurate) of adjusting the VDD fault voltage is to use a resistive network of R3 from
the pin to supply and R4 from the pin to ground (see applications diagram). In order to set the new threshold
voltage, the equivalent resistance must be determined. This resistance value will be designated Kx. Kx is
defined as R4/(R4+R5). Kx is calculated as:
Kx = (2.649 / VTH) - 0.6042 where VTH is the desired new threshold voltage.
To determine the values of R4 and R5, use the following formulas.
R5 = 72000 / Kx
R4 = R5*(Kx / (1 – Kx))
Taking the example above, where a VDD fault threshold voltage of 2.7V is desired, solving for Kx gives:
Kx = (2.649 / 2.7) - 0.6042 = 0.377.
Solving for R5 gives:
R5 = 72000 / 0.377 = 191K
.
Solving for R4 gives:
R4 = 191000 *(0.377 / (1 – 0.377)) = 115.6 K
.
Using standard 1 % resistor values gives R5 = 191K
and R4 = 115K.
These values give an equivalent resistance of Kx = 0.376, a 0.3% error.
If the 2.3V default threshold is used, this pin must be left unconnected.
POWER DOWN
A power-down function is provided via the pin PWRDN (Active High). When activated, the Power Down (PD)
mode disables all the internal analog functions, including the card analog interface, the oscillators and the DC-DC
converter, to put the 73S8010C in its lowest power consumption mode. PD mode is only allowed in the de-
activated condition (out of a card session, when the Start/Stop bit is set to 0 from the I
2C host controller). Power-
down state is invoked by the host controller as required when it is deemed desirable to save power. The signal
PRES remains functional in PD mode such that a card insertion sets
INT high. The micro-controller must then set
PWRDN low and wait for the internal stabilization time prior to starting any card session (prior to setting the
Start/Stop bit to 1). Resumption of the normal mode occurs at approximately 10ms (stabilization of the internal
oscillators + reset of the circuitry) after PWRDN is set low. No card activation should be invoked during this 10ms
time period. If a card is present,
INT can be used as an indication that the circuit has completed its recovery from
power-down state.
INT will go high at the end of the stabilization period. Should the Start/Stop be set to 1 during
PWRDN = 1, or within the 10ms internal stabilization / reset time, it will not be taken into account and the card
interface will remain inactive. Since Start/Stop is taken into account on its edges, it should be toggled low and
high again after the 10ms to activate a card. Figure 2 illustrates the sequencing of the PD and Normal modes.
Note: PWRDN must be connected to GND if power down function is not used.