t1
參數(shù)資料
型號(hào)： 73S8010R-IMR/F
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 13/25頁(yè)
文件大小： 0K
描述： IC SMART CARD INTERFACE 32-QFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
控制器類型： 智能卡接口
接口： I²C
電源電壓： 2.7 V ~ 5.5 V
電流 - 電源： 1.5mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 32-QFN（5x5）
包裝： 帶卷 (TR)
73S8010R Data Sheet
DS_8010R_022
20
Rev. 1.6
Start/Stop
RST
CLK
IO
VCC
t
1
t
2
t
3
t
4
t1 = > .5
μs
t2 = > 7.5
μs
t3 = > 0.5
μs
t4 = > 0.5
μs
Figure 9: Deactivation Sequence
3.9
Interrupt
The Interrupt is an active low interrupt. It is set low if any of the following internal faults are detected:
VCC fault
VDD fault
VPC fault
The interrupt will also be set if one of the following status bit conditions is detected:
Early ATR
Mute ATR
Card insert or card extract
Protection status from Over-current or Over-heating
When the interrupt is set low by the detection of one of the status bits, it is set high when the status bits
are read. (READ STATUS DONE) Figure 10 shows the interrupt operation resulting from the fault or
status bit conditions.
Figure 10: Interrupt operation due to Fault and Status Conditions
A power-on-reset event will reset all of the control and status registers to their default states. A VDD fault
event does not reset these registers, but it will signal an interrupt condition and by the action of the timer
that creates the interval “t1,” not clearing the interrupt until VDD is valid for at least t1. A VDD fault can be
considered valid for VDD as low as 1.5 to 1.8 volts. At the lower range of VDD fault, POR will be asserted.
INT
ANY FAULT
STATUS BITS
READ STATUS DONE
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