參數資料
型號: 73S8023C-IMR
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 模擬信號調理
英文描述: SPECIALTY ANALOG CIRCUIT, QCC32
封裝: 5 X 5 MM, QFN-32
文件頁數: 5/27頁
文件大?。?/td> 389K
代理商: 73S8023C-IMR
DS_8023C_019
73S8023C Data Sheet
Rev. 1.5
13
Figure 5: Asynchronous Activation Sequence – RSTIN Low When
CMDVCC Goes Low
The following steps list the activation sequence and the timing of the card control signals when the
system controller pulls the
CMDVCC low while the RSTIN is high:
1.
CMDVCC is set low.
2.
Next, the internal VCC control circuit checks the presence of VCC at t1. In normal operation, the
voltage VCC to the card becomes valid during this time. If not, OFF goes low to report a fault to the
system controller, and the power VCC
3.
Due to the fall of RSTIN at t
to the card is turned off.
2
4.
CLK is applied to the card at the end of t
, turn I/O (AUX1, AUX2) to reception mode.
3
5.
RST is to be a copy of RSTIN after t
after I/O is in reception mode.
4. RSTIN may be set high before t 4, however the sequencer
won’t set RST high until 42000 clock cycles after the start of CLK.
CMDVCC
VCC
IO
CLK
RSTIN
t1
t2
t3
t4
RST
t1 = 0.510 ms (timing by 1.5MHz internal Oscillator)
t2 = 1.5s, I/O goes to reception state
t3 = > 0.5s, CLK active
t4
Figure 6: Asynchronous Activation Sequence – Timing Diagram #2
≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
CMDVCC
VCC
IO
CLK
RSTIN
t1
t2
t3
t4
RST
t1 = 0.510 ms (timing by 1.5 MHz internal Oscillator)
t2 = 1.5 s, I/O goes to reception state
t3
≥ 0.5 s, CLK starts
t4
≥ 42000 card clock cycles. Time for RST to become the copy of RSTIN
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