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參數(shù)資料
| 型號(hào)： | 73S8024C-IL/F |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 19/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SMART CARD INTERFACE 28-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 控制器類型： | 智能卡接口 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC |
| 包裝： | 管件 |
73S8024C Data Sheet
DS_8024C_023
6
Rev. 1.3
2
System Controller Interface
2 digital inputs allow direct control of the card interface from the host as follows:
Pin
CMDVCC: When low, starts an activation sequence if a card is present.
Pin 5V/
#V: Defines the card voltage.
The card I/O and Reset signals have their corresponding controller I/Os to be connected directly to
the host:
Pin RSTIN: controls the card reset signal (when enabled by the sequencer).
Pin I/OUC: data transfer to card I/O contact.
Pins AUX1UC and AUX2UC (auxiliary I/O lines associated to the auxiliary I/O lines to be
connected to the C4 and C8 card connector contacts).
2 digital inputs control the card clock frequency division rate: CLKDIV1 and CLKDIV2 define the card
clock frequency, from the input clock frequency (crystal or external clock). The division rate is defined
as follows:
CLKDIV2
CLKDIV1
CLK
0
XTAL
0
1
XTAL
1
0
XTAL
1
XTAL
When the division rate is equal to 1 (CLKDIV2 =0 and CLKDIV1 = 1), the duty-cycle of the
card clock depends on the duty-cycle and waveform of the signal applied on the pin XTALIN.
When other division rates are used, the 73S8024C circuitry guarantees a duty-cycle in the
range 45% to 55%, conforming to ISO-7816-3, EMV 4.0 and NDS specifications.
Interrupt output to the host: As long as the card is not activated, the
OFF pin informs the host about
the card presence only (low = no card in the reader). When
CMDVCC is set low (Card activation
sequence requested from the host), a low level on
OFF means a fault has been detected (e.g. card
removed during a card session, or voltage fault, or thermal / over-current fault) that automatically
initiates a deactivation sequence.
Power Down: The PWRDN pin is a digital input that allows the host controller to put the 73S8024C in
its Power Down state. This pin can only be activated out of a card session.
3
Oscillator
The 73S8024C device has an on-chip oscillator that can generate the smart card clock using an external
crystal (connected between the pins XTALIN and XTALOUT) to set the oscillator frequency. When the
card clock signal is available from another source, it can be connected to the pin XTALIN, and the pin
XTALOUT should be left unconnected.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73S8024C-ILR/F | 功能描述:輸入/輸出控制器接口集成電路 Smart Card Interface ISO7816-3 & EVM4.0 RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| 73S8024RN | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Low Cost Smart Card Interface |
| 73S8024RN-20IM/F | 功能描述:輸入/輸出控制器接口集成電路 Smart Card Interface ISO7816-3 & EVM4.0 RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| 73S8024RN-20IM/F1 | 功能描述:輸入/輸出控制器接口集成電路 Smart Card Interface ISO7816-3 & EVM4.0 RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| 73S8024RN-20IMR/F | 功能描述:輸入/輸出控制器接口集成電路 Smart Card Interface ISO7816-3 & EVM4.0 RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
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