參數(shù)資料
型號(hào): 73S8024RN-DB
廠商: Maxim Integrated Products
文件頁數(shù): 7/27頁
文件大小: 0K
描述: BOARD DEMO 73S8024RN 28-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
系列: *
DS_8024RN_020
73S8024RN Data Sheet
Rev. 2
15
11 Typical Application Schematic
SO28
See NOTE 4
VDD
CLKSTOP_from_uC
Y1
CRYSTAL
C2
22pF
C1
NDS & ISO7816=1uF, EMV=3.3uF
See NOTE 5
RSTIN_from_uC
CLKDIV2_from_uC
CLK track should be routed
far from RST, I/O, C4 and
C8.
NOTES:
1) VDD = 2.7V to 5.5V DC.
2) VPC = 4.75V(EMV, ISO)/4.85(NDS) to 5.5V DC
3) Required if external clock from uP is used.
4) Required if crystal is used.
Y1, C2 and C3 must be removed if external clock is used.
5) Optional. Can be left open.
6)Internal pull-up allows it to be left open if unused.
7) R1 and R3 are external resistors that adjust the VDD
fault voltage. Can be left open.
I/OUC_to/from_uC
R1
Rext1
See NOTE 1
Card detection
switch is
normally closed
VPC
C6
100nF
VDD
External_clock_from uC
C4
100nF
C3
22pF
AUX1UC_to.from_uC
See NOTE 5
C5
10uF
AUX2UC_to/from_uC
See NOTE 3
See NOTE 2
CLKLVL_from_uC
VDD
Low ESR (<100mohms) C1
should be placed near the SC
connecter contact
CLKDIV1_from_uC
CMDVCC_from_uC
73S8024RN
1
2
3
4
5
6
7
12
8
9
10
11
13
14
15
16
17
18
19
20
21
22
23
28
27
25
24
26
CLKDIV1
CLKDIV2
5V3V_
GND
NC
VPC
CLKSTOP
AUX2
CLKLVL
PRESB
PRES
I/O
AUX1
GND
CLK
RST
VCC
VDDF_ADJ
CMDVCC_
RSTIN
VDD
GND
OFF_
AUX2UC
AUX1UC
XTALOUT
XTALIN
I/OUC
5V/3V_select_from_uC
OFF_interrupt_to_uC
R3
Rext2
- OR -
R2
20K
See note 7
Smart Card Connector
1
2
3
4
5
6
7
8
9
10
VCC
RS
T
CLK
C4
G
ND
VPP
I/O
C8
SW
-1
SW
-2
See NOTE 6
VDD
Figure 8: 73S8024RN – Typical Application Schematic
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