參數(shù)資料
型號: 7404
廠商: 意法半導(dǎo)體
英文描述: TRIPLE VOLTAGE REGULATOR
中文描述: 三電壓調(diào)節(jié)器
文件頁數(shù): 3/11頁
文件大?。?/td> 287K
代理商: 7404
ST3M01
3/11
CONNECTION DIAGRAM
(top view)
PIN DESCRIPTION
Pin N°
Symbol
Name and Function
1
2
3
GND SW
GND SW
Virtual GND
Switching Ground. Must be low impedance; solder directly to GND plane
Switching Ground. Must be low impedance; solder directly to GND plane
Virtual GND. Open Drain N-Cnannel MOSFET: must be high impedance when the
Low Battery condition is detected.
Low Battery Output. Open Drain N-Cnannel MOSFET: sinks current when the
input voltage drops below 2V typically.
Reference Voltage Output. Bypass with 0.1
μ
F to improve the linears V
REF
thermal noise performance
.
Linear Input. Must be connected togheter with IN SW to the input supply.
Linear B Output port. 1.9V typically.
Shutdown Input. Disables the SMPS and
L
A
output, but the
L
B
, the
referencevoltage and the low batery comparator remain active.
Signal GND. Must be connected togheter with the Switching Ground.
Linear A Output port. 3V typically.
DC/DC Output Port: 3.3V typically.
SMPS Input. Must be connected togheter with IN_Linear to the input supply.
1.5A N-Channel Power MOSFET Drain.
1.5A N-Channel Power MOSFET Drain.
4
LBO
5
V
REF
6
7
8
IN Linear
OUT L
B
SHDN
9
GND Signal
OUT L
A
OUT DC/DC
IN SW
LX
LX
10
11
12
13
14
相關(guān)PDF資料
PDF描述
7404 Package contains six inverters
7405 3/4 DIAMETER WIRE-WOUND, MULTI-TURN
7409 Quad 2-Input AND Gates with Open-Collector Outputs
74107 DUAL J-K FLIP FLOP WITH CLEAR
7410 Triple 3-Input NAND Gates
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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