參數(shù)資料
型號: 74112
廠商: 意法半導體
英文描述: DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
中文描述: 雙JK觸發(fā)器亂竄預置和清除
文件頁數(shù): 1/11頁
文件大?。?/td> 251K
代理商: 74112
M54HC112
M74HC112
October 1992
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
LOWPOWER DISSIPATION
I
CC
= 2
μ
AAT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS112
B1R
(Plastic Package)
ORDER CODES :
M54HC112F1R
M74HC112B1R
M74HC112M1R
M74HC112C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
DESCRIPTION
The M54/74HC112 isa high speed CMOSDUAL J-K
FLIP-FLOPWITHPRESET ANDCLEAR fabricated in
silicon gate C
2
MOStechnology. It has the same high
speed performance of LSTTL combined with true
CMOS
low
power
M54HC112/M74HC112 dual JK flip-flop features indi-
vidualJ,K,clock,andasynchronous setandclearinputs
foreach flip-flop. When the clockgoes high, the inputs
are enabled and data will be accepted. The logic level
oftheJ and Kinputs may be allowed to change when
the clockpulse is high and the bistable will function as
shown in the truth table. Input data istransferred to the
input on the negative going edge of theclockpulse. All
inputsareequipped withprotectioncircuitsagainststatic
discharge and transient excessvoltage.
.
HIGH SPEED
f
MAX
= 67 MHz (TYP.) AT V
CC
= 5 V
consumption.
The
1/11
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