參數(shù)資料
型號: 7429
廠商: 意法半導體
英文描述: 3 BAND EQUALIZER AUDIO PROCESSOR WITH SUBWOOFER CONTROL
中文描述: 3波段均衡器音頻處理器低音炮控制
文件頁數(shù): 6/16頁
文件大小: 114K
代理商: 7429
TDA7429L
6/16
1.0 I
2
C BUS INTERFACE
Data transmission from microprocessor to the TDA7429L and viceversa takes place through the 2 wires I
2
C
BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be
connected).
1.1 Data Validity
As shown in fig. 3, the data on the SDA line must be stable during the high period of the clock. The HIGH and
LOW state of the data line can only change when the clock signal on the SCL line is LOW.
1.2 Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop
condition is a LOW to HIGH transition of the SDA line while SCL is HIGH.
1.3 Byte Format
Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transferred first.
1.4 Acknowledge
The master (mP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 5).
The peripheral (audioprocessor) that acknowledges has to pull-down (LOW) the SDA line during this clock
pulse.
The audioprocessor which has been addressed has to generate an acknowledge after the reception of each
byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master
transmitter can generate the STOP information in order to abort the transfer.
1.5 Transmission without Acknowledge
Avoiding to detect the acknowledge of the audioprocessor, the
μ
P can use a simpler transmission: simply it
waits one clock without checking the slave acknowledging, and sends the new data.
This approach of course is less protected from misworking.
Figure 4. Data validity on the I
2
C bus
Figure 5. Timing Diagram of I
2
C bus
SDA
SCL
DATA
LINE
STABLE,DAT
A
VALID
CHANGE
DAT
A
ALLOWED
D99AU1031
SCL
SDA
START
I
2
CBUS
STOP
D99AU1032
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