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參數(shù)資料
| 型號： | 7431 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | DIGITALLY CONTROLLED AUDIO PROCESSOR WITH SURROUND SOUND MATRIX AND VOICE CANCELLER |
| 中文描述： | 數(shù)控式環(huán)繞聲矩陣和消音器的音頻處理器 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 168K |
| 代理商： | 7431 |
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7430/TDA7431 and viceversa takes place
through the 2 wires I
2
C BUS interface, consisting
of the two lines SDA and SCL (pull-up resistors to
positive supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferredon the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
Figure 3:
Data Validityon theI
2
CBUS
knowledgebit. The MSB is transferredfirst.
Acknowledge
The master (
μ
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
duringthisclock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor,the
μ
P can use a simpler transmission:
simply it waits one clock without checking the
slaveacknowledging,and sends the new data.
This approach of course is less protected from
misworking.
Figure 4:
TimingDiagram of I
2
CBUS
F
igure 5:
Acknowledgeon the I
2
CBUS
TDA7430 - TDA7431
9/21
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