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參數(shù)資料
| 型號： | 7442 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | BCD to Decimal Decoder |
| 中文描述： | BCD碼的十進(jìn)制譯碼器 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 218K |
| 代理商： | 7442 |
I
2
C BUS INTERFACE
Data transmission from microprocessor to the
TDA7442D and viceversa takes place through the
2 wires I
2
C BUS interface, consisting of the two
lines SDA and SCL (pull-up resistors to positive
supply voltage must be connected).
Data Validity
As shown in fig. 3, the data on the SDA line must
be stable during the high period of the clock. The
HIGH and LOW state of the data line can only
change when the clock signal on the SCL line is
LOW.
Start and Stop Conditions
As shown in fig.4 a start condition is a HIGH to
LOW transition of the SDA line while SCL is
HIGH. The stop condition is a LOW to HIGH tran-
sition of the SDA line while SCL is HIGH.
Byte Format
Every byte transferred on the SDA line must con-
tain 8 bits. Each byte must be followed by an ac-
Figure 3:
Data Validity on the I
2
CBUS
knowledge bit. The MSB is transferred first.
Acknowledge
The master (
μ
P) puts a resistive HIGH level on the
SDA line during the acknowledge clock pulse (see
fig. 5). The peripheral (audioprocessor) that ac-
knowledges has to pull-down (LOW) the SDA line
during this clock pulse.
The audioprocessor which has been addressed
has to generate an acknowledge after the recep-
tion of each byte, otherwise the SDA line remains
at the HIGH level during the ninth clock pulse
time. In this case the master transmitter can gen-
erate the STOP information in order to abort the
transfer.
Transmission without Acknowledge
Avoiding to detect the acknowledge of the audio-
processor, the
μ
P can use a simpler transmission:
simply it waits one clock without checking the
slave acknowledging, and sends the new data.
This approach of course is less protected from
misworking.
SDA
SCL
DATA LINE
STABLE, DATA
VALID
CHANGE
DATA
ALLOWED
D99AU1031
SCL
SDA
START
I
2
CBUS
STOP
D99AU1032
Figure 4:
Timing Diagram of I
2
CBUS
SCL
1
MSB
2
3
7
8
9
SDA
START
ACKNOWLEDGMENT
FROM RECEIVER
D99AU1033
F
igure 5:
Acknowledge on the I
2
CBUS
TDA7442 - TDA7442D
6/16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 7446A | BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS |
| 7446A | BCD to 7-Segment Decoders/Drivers |
| 7446A | BCD to 7-Segment Decoders/Drivers |
| 7447 | BCD TO 7-SEGMENT DECODER-DRIVER(Low=on, 40-mA, 30-Volt Outputs) |
| 7448 | Dcvice converts BCD input data into control signals for 7-segment displays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 744-2 | 制造商:TE Connectivity / AMP 功能描述: |
| 7442 WAF | 制造商:Fairchild Semiconductor Corporation 功能描述: 制造商:Texas Instruments 功能描述: |
| 744201 | 制造商:WURTH 制造商全稱:Wurth Elektronik GmbH & Co. KG, Germany. 功能描述:WE-SL SMD Common Mode Line Filter |
| 744201-000 | 制造商:TE Connectivity 功能描述:ADPTR TINEL LOCK STR SHELL 13, C 制造商:TE Connectivity 功能描述:Connector Accessories Cable Termination Adapters Braided Or Magneform Aluminum Alloy Olive Drab |
| 7-442-01E-BA | 功能描述:HEATSINK PWR HORZ .75"H TO-3 RoHS:是 類別:風(fēng)扇，熱管理 >> 熱敏 - 散熱器 系列:7 產(chǎn)品目錄繪圖:BDN12-3CB^A01 標(biāo)準(zhǔn)包裝:300 系列:BDN 類型:頂部安裝 冷卻式包裝:分類（BGA，LGA，CPU，ASIC……） 固定方法:散熱帶，粘合劑（含） 形狀:方形，鰭片 長度:1.21"（30.73mm） 寬:1.210"（30.73mm） 直徑:- 機(jī)座外的高度（散熱片高度）:0.355"（9.02mm） 溫升時的功耗:- 在強(qiáng)制氣流下的熱敏電阻:在 400 LFM 時為6.8°C/W 自然環(huán)境下的熱電阻:19.6°C/W 材質(zhì):鋁 材料表面處理:黑色陽極化處理 產(chǎn)品目錄頁面:2681 (CN2011-ZH PDF) 其它名稱:294-1099 |
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