參數(shù)資料
型號: 74ABT899CQC
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: 9-Bit Latchable Transceiver with Parity Generator/Checker
中文描述: ABT SERIES, 9-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PQCC28
封裝: 0.450 X 0.450 INCH, MO-047, PLASTIC, LCC-28
文件頁數(shù): 3/16頁
文件大?。?/td> 123K
代理商: 74ABT899CQC
Philips Semiconductors
Product specification
74ABT899
9-bit dual latch transceiver with 8-bit parity
generator/checker (3-State)
1998 Jan 16
3
PIN CONFIGURATION
3
4
5
6
7
8
9
10
11
12
17
18
19
20
21
22
23
24
25
26
LEA
A0
A1
A2
A3
A4
A5
A6
A7
BPAR
APAR
B7
B6
B5
B4
B3
B2
B1
B0
LEB
13
16
OEA
SEL
14
15
GND
ERRB
TOP VIEW
1
2
27
28
ODD/EVEN
ERRA
OEB
V
CC
SA00289
PIN DESCRIPTION
SYMBOL
PIN
NUMBER
NAME AND FUNCTION
A0 - A7
4, 5, 6, 7,
8, 9, 10,
11
Latched A bus 3-State inputs/outputs
B0 - B7
19, 20,
21, 22,
23, 24,
25, 26
Latched B bus 3-State inputs/outputs
APAR
12
A bus parity 3-State input
BPAR
18
B bus parity 3-State input
ODD/
EVEN
1
Parity select input (Low for EVEN
parity)
OEA, OEB
13, 27
Output enable inputs (gate A to B,
B to A)
SEL
16
Mode select input (Low for generate)
LEA, LEB
3, 17
Latch enable inputs (transparent High)
ERRA,
ERRB
2, 15
Error signal outputs (active-Low)
GND
14
Ground (0V)
V
CC
28
Positive supply voltage
PLCC PIN CONFIGURATION
3
4
5
17
18
28
LEA
A0
A1
A2
A3
A4
A5
A6
A7
BPAR
V
CC
ODD/
EVEN
ERRA
LEB
16 SEL
15 ERRB
1
2
27
26
OEB
B0
6
7
8
9
10
11
13
14 GND
OEA
12 APAR
25
B1
B2
24
B3
23
B4
22 21
B5
B6
20
B7
19
SA00291
LOGIC SYMBOL
4
5
6
7
8
9
10
11
A0 A1 A2 A3 A4 A5 A6 A7
B0 B1 B2 B3 B4 B5 B6 B7
26 25 24 23
22 21 20 19
2
15
3
16
17
1
LEA
SEL
LEB
ODD/EVEN
ERRA
ERRB
12
APAR
BPAR
18
27
13
OEB
OEA
SA00290
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