參數(shù)資料
型號: 74AC11074PW
廠商: Texas Instruments, Inc.
元件分類: 通用總線功能
英文描述: DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET
中文描述: 雙上升沿觸發(fā)的D型倒裝有明確和預(yù)設(shè)次浮點運算
文件頁數(shù): 4/6頁
文件大?。?/td> 92K
代理商: 74AC11074PW
74AC11074
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
SCAS499A – DECEMBER 1986 – REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (see Figure 1)
TA = 25
°
C
MIN
MIN
MAX
UNIT
MAX
fclock
Clock frequency
0
100
0
100
MHz
tw
Pulse duration
PRE or CLR low
4
4
ns
CLK low or high
5
5
tsu
Set p time before CLK
Setup time before CLK
Data high or low
5
5
ns
PRE or CLR inactive
1
1
th
Hold time after CLK
0
0
ns
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (see Figure 1)
TA = 25
°
C
MIN
MIN
MAX
UNIT
MAX
fclock
Clock frequency
0
125
0
125
MHz
tw
Pulse duration
PRE or CLR low
4
4
ns
CLK low or CLK high
4
4
tsu
Set p time before CLK
Setup time before CLK
Data high or low
3.5
3.5
ns
PRE or CLR inactive
1
1
th
Hold time after CLK
0
0
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V
±
0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
TA = 25
°
C
TYP
MIN
MAX
UNIT
(OUTPUT)
MIN
MAX
fmax
tPLH
tPHL
tPLH
tPHL
100
125
100
MHz
PRE or CLR
Q or Q
1.5
5.8
9.3
1.5
10
ns
1.5
6.5
11.4
1.5
12.2
CLK
Q or Q
1.5
7.7
10.5
1.5
11.3
ns
1.5
7.3
9.7
1.5
10.6
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
TA = 25
°
C
TYP
MIN
MAX
UNIT
(OUTPUT)
MIN
MAX
fmax
tPLH
tPHL
tPLH
tPHL
125
150
125
MHz
PRE or CLR
Q or Q
1.5
4.2
6.6
1.5
7.1
ns
1.5
4.7
8.2
1.5
9
CLK
Q or Q
1.5
5.4
7.5
1.5
8.2
ns
1.5
5
6.9
1.5
7.5
operating characteristics, V
CC
= 5 V, T
A
= 25
°
C
PARAMETER
TEST CONDITIONS
TYP
UNIT
Cpd
Power dissipation capacitance
CL = 50 pF,
f = 1 MHz
30
pF
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