參數(shù)資料
型號(hào): 74AC11881
廠商: Texas Instruments, Inc.
英文描述: Arithmetic Logic Units/Fuction Generators(算術(shù)邏輯單元/函數(shù)發(fā)生器)
中文描述: 算術(shù)邏輯單元/作用分析發(fā)生器(算術(shù)邏輯單元/函數(shù)發(fā)生器)
文件頁(yè)數(shù): 18/19頁(yè)
文件大?。?/td> 236K
代理商: 74AC11881
tPLH
Ai
Bi
None
None
None
None
Bi
Ai
Cn+4
Cn+4
Cn+4
Cn+4
Out-of-Phase
Out-of-Phase
In-Phase
In-Phase
Ai
Ai
None
None
None
None
Bi
Bi
tPHL
tPHL
tPLH
Ai
Ai
Bi
Bi
Bi
Bi
Ai
Ai
None
None
None
None
Fi
Fi
Fi
Fi
tPLH
tPHL
tPLH
tPHL
Out-of-Phase
Out-of-Phase
None
None
None
None
Out-of-Phase
Out-of-Phase
54AC11881, 74AC11881
ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
18
PARAMETER MEASUREMENT INFORMATION
DIFF Mode Test Table (Continued)
FUNCTION INPUTS: S1 = S2 = 4.5 V, S0 = S3 = M = 0 V
INPUT
UNDER
TEST
Cn
Cn
OTHER INPUT SAME BIT
APPLY
4.5 V
None
None
OTHER DATA INPUTS
APPLY
4.5 V
All A and B
All A and B
OUTPUT
UNDER
TEST
Cn+4 or Any F
Cn+4 or Any F
OUTPUT
WAVEFORM
(SEE NOTE 2)
In-Phase
In-Phase
PARAMETER
APPLY
GND
None
None
APPLY
GND
None
None
Remaining A,
B, Cn
Remaining A,
B, Cn
Remaining A,
B, Cn
Remaining A,
B, Cn
tPLH
tPHL
Logic Mode Test Table
FUNCTION INPUTS: S1 = S2 = M = 4.5 V, S0 = S3 = 0 V
INPUT
UNDER
TEST
OTHER INPUT SAME BIT
APPLY
4.5 V
OTHER DATA INPUTS
APPLY
4.5 V
OUTPUT
UNDER
TEST
OUTPUT
WAVEFORM
(SEE NOTE 2)
PARAMETER
APPLY
GND
APPLY
GND
Remaining A
and B, Cn
Remaining A,
and B, Cn
Remaining A,
and B, Cn
Remaining A,
and B, Cn
NOTE 2: Load circuits and voltage waveforms are shown in Section 1 of Advanced CMOS Logic Data Book, 1990.
P
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