54ACT11190, 74ACT11190
SYNCHRONOUS 4-BIT UP/DOWN DECADE COUNTERS
SCAS383 – MARCH 1990
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Copyright
1990, Texas Instruments Incorporated
1
Inputs Are TTL-Voltage Compatible
Single Down/Up Count Control Line
Look-Ahead Circuitry Enhances Speed of
Cascaded Counters
Fully Synchronous in Count Modes
Asynchronously Presettable With Load
Control
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1- m Process
500-mA Typical Latch-Up Immunity
at 125
°
C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and
Ceramic 300-mil DIPs
description
The ’ACT11190 is a synchronous, 4-bit decade
reversable up/down counter. Synchronous
counting operation is provided by having all
flip-flops clocked simultaneously so that the
outputs change coincident with each other when
so instructed by the steering logic.This mode of
operation eliminates the output counting spikes
normally
associated
(ripple-clock) counters.
with
asynchronous
The outputs of the four flip-flops are triggered on
a low-to-high transition of the clock input if the
enable input (CTEN) is low. A high at CTEN
inhibits counting. The direction of the count is
determined by the level of the down/up (D/U)
input. When the D/U input is low, the counter
counts up. When the D/U input is high, the counter
counts down.
These counters feature a fully independent clock
circuit. Changes at control inputs (CTEN and D/U)
that will modify the operating mode have no effect
on the contents of the counter until clocking
occurs. The function of the counter is dictated
solely by the condition meeting the stable setup
and hold times.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
RCO
Q
A
Q
B
GND
GND
GND
GND
Q
C
Q
D
MAX/MIN
54ACT11190 . . . J PACKAGE
74ACT11190 . . . DW OR N PACKAGE
(T0P VIEW)
3
2
1 20 19
9 10 11 12 13
4
5
6
7
8
18
17
16
15
14
D
CTEN
LOAD
MAX/MIN
Q
D
CLK
D/U
RCO
Q
A
Q
B
54ACT11190 . . . FK PACKAGE
(T0P VIEW)
A
B
V
G
Q
V
C
G
G
G
logic symbol
B
12
20
18
17
13
14
11
19
CLK
C
D
A
G1
M2 [DOWN]
M3 [UP]
1,2–/1,3+
G4
C5
9
8
3
2
6,1,4
3(CT=9)Z6
2(CT=0)Z6
CTRDIV10
RCO
MAX/MIN
10
1
5D
[1]
[2]
[4]
[8]
CTEN
LOAD
D/U
QA
QB
QC
QD
This symbol is in accordance with ANSI/IEEE Std. 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for DW, J, and N packages.
D/U
CLK
A
B
V
CC
V
CC
C
D
CTEN
LOAD
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
P
EPIC is a trademark of Texas Instruments Incorporated.