
INPUT AND OUTPUT EQUIVALENT CIRCUIT
LOGIC DIAGRAMS
PIN DESCRIPTION
PIN No
1
2
SYMBOL
CLEAR
CLOCK
NAME AND FUNCTION
Master Reset
ClockInput (LOW-to-HIGH,
Edge- Triggered)
DataInputs
CountEnable Input
CountEnable Carry Input
Parallel Enable Input
Flip-Flop Outpus
3, 4, 5, 6
7
10
9
14, 13, 12,
11
15
A, B, C, D
PE
TE
LOAD
QA to QD
CARRY
OUT
GND
V
CC
Terminal Count Output
8
Ground (0V)
Positive Supply Voltage
16
TRUTH TABLE
INPUTS
PE
X
X
X
L
H
X
OUTPUTS
QB
L
B
NO CHANGE
NO CHANGE
COUNT UP
NO CHANGE
FUNCTION
CLEAR
L
H
H
H
H
H
NOTE:
LOAD
X
L
H
H
H
X
X:Don’tCare
A,B,C,D: Logiclevelofdatainput
CARRY=TE
QA
QB
QC
QD
TE
X
X
L
X
H
X
CLOCK
X
QA
L
A
QC
L
C
QD
L
D
RESET TO ”0”
PRESET DATA
NO COUNT
NO COUNT
COUNT
NO COUNT
74ACT161
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