參數(shù)資料
型號(hào): 74ACT16841DGG
廠商: Texas Instruments, Inc.
元件分類: 通用總線功能
英文描述: 20-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS
中文描述: 20位總線接口D型鎖存器具有三態(tài)輸出
文件頁數(shù): 4/6頁
文件大?。?/td> 113K
代理商: 74ACT16841DGG
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25
°
C
TYP
54ACT16841
MIN
4.4
74ACT16841
MIN
4.4
UNIT
MIN
4.4
MAX
MAX
MAX
IOH= 50
μ
IOH =–50
A
4.5 V
5.5 V
5.4
5.4
5.4
VOH
IOH= 24 mA
IOH = –24 mA
4.5 V
3.94
3.8
3.8
V
5.5 V
4.94
4.8
4.8
IOH = –75 mA
5.5 V
3.85
3.85
IOL= 50
μ
IOL = 50
A
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
VOL
IOL= 24 mA
IOL = 24 mA
4.5 V
0.36
0.44
0.44
V
5.5 V
0.36
0.44
0.44
IOL = 75 mA
VI = VCC or GND
VO = VCC or GND
VI = VCC or GND,
One input at 3.4 V,
Other inputs at VCC or GND
VI = VCC or GND
VO = VCC or GND
5.5 V
1.65
±
1
±
5
80
1.65
±
1
±
5
80
II
IOZ
ICC
5.5 V
±
0.1
±
0.5
μ
A
μ
A
μ
A
5.5 V
IO = 0
5.5 V
8
ICC
5.5 V
0.9
1
1
mA
Ci
Co
5 V
3
pF
5 V
11
pF
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
TA = 25
°
C
MIN
54ACT16841
MIN
74ACT16841
MIN
UNIT
MAX
MAX
MAX
tw
tsu
Pulse duration, LE high
Setup time, data before LE
4
4
4
ns
1.5
1.5
1.5
ns
th
Hold time data after LE
Hold time, data after LE
High
3
3
3
ns
Low
4.5
4.5
4.5
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
TA = 25
°
C
TYP
54ACT16841
MIN
4
74ACT16841
MIN
4
UNIT
(OUTPUT)
MIN
MAX
10.3
MAX
11.8
MAX
11.8
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
D
Q
4
7.1
ns
3.2
6.9
11
3.2
12.2
3.2
12.2
LE
Q
4.5
7.7
11.3
4.5
12.7
4.5
12.7
ns
4.3
7.8
11.4
4.3
12.7
4.3
12.7
OE
Q
3.1
6.4
10.1
3.1
11.3
3.1
11.3
ns
3.8
7.6
12.1
3.8
13.7
3.8
13.7
OE
Q
4
7.3
9.5
4
10.2
4
10.2
ns
4
6.8
8.9
4
9.6
4
9.6
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
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