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參數(shù)資料
| 型號： | 74ACT2708PC |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | DRAM |
| 英文描述： | 64 x 9 First-In, First-Out Memory |
| 中文描述： | 64 X 9 OTHER FIFO, 34.5 ns, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, MS-010, DIP-28 |
| 文件頁數(shù)： | 5/13頁 |
| 文件大?。?/td> | 95K |
| 代理商： | 74ACT2708PC |
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www.fairchildsemi.com
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Mode 2: Master Reset
Sequence of Operation
1. Input and Output Ready, HF and FULL can be in any
state before the reset sequence with Master Reset
(MR) HIGH.
2. Master Reset goes LOW and clears the FIFO, setting
up all essential internal states. Master Reset must be
LOW pulse width t
MRW
before rising again.
3. Master Reset rises.
4. IR rises (if not HIGH already) to indicate ready to write
state recovery time t
MRIRH
after the falling edge of MR.
Both HF and FULL will go LOW indicating an empty
FIFO, occurring recovery times t
MRE
and t
MRO
respec-
tively after the falling edge of MR. OR falls recovery
time t
MRORL
after MR falls. Data at outputs goes LOW
recovery time t
MRONL
after MR goes LOW.
5. Shift-In can be taken HIGH after a minimum recovery
time t
MRSIH
after MR goes HIGH.
FIGURE 2. Mode of Operation Mode 2
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