參數(shù)資料
型號: 74ACT280
廠商: 意法半導(dǎo)體
英文描述: 9 BIT PARITY GENERATOR/CHECKER
中文描述: 9位奇偶產(chǎn)生器/校驗器
文件頁數(shù): 1/8頁
文件大?。?/td> 63K
代理商: 74ACT280
74ACT280
9 BIT PARITY GENERATOR/CHECKER
December 1998
I
HIGHSPEED:t
PD
=4ns(TYP.)atV
CC
=5V
I
LOWPOWERDISSIPATION:
I
CC
=4
μ
A(MAX.) at T
A
=25
o
C
I
COMPATIBLEWITH TTL OUTPUTS
V
IH
=2V (MIN),V
IL
= 0.8V(MAX)
I
50
TRANSMISSIONLINEDRIVING
CAPABILITY
I
SYMMETRICALOUTPUTIMPEDANCE:
|I
OH
| = I
OL
= 24mA(MIN)
I
BALANCEDPROPAGATIONDELAYS:
t
PLH
t
PHL
I
OPERATINGVOLTAGERANGE:
V
CC
(OPR)= 4.5Vto 5.5V
I
PINANDFUNCTION COMPATIBLEWITH
74SERIES280
I
IMPROVEDLATCH-UP IMMUNITY
DESCRIPTION
The AC280 is an advanced high-speed CMOS 9
BIT
PARITY
GENERATOR
fabricated with sub-micron silicon gate
double-layermetal wiring C
2
MOS technology.It is
ideal for low power applications mantaining high
speed operation similar to eqivalent Bipolar
SchottkyTTL.
It is composed of nine data inputs (A to I) and
odd/evenparity outputs (
Σ
ODD and
Σ
EVEN). The
-
CHECKER
and
nine data inputs control the output conditions.
When the number of high level input is odd,
Σ
ODD output is kept high and
Σ
EVEN output low.
Conservely, when the output is even,
Σ
EVEN
outputis kept high and
Σ
ODDlow.
The IC generates either odd or even parity
making it flexibleapplication.
The word-length capability is easily expanded by
cascading.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All
inputs
and
outputs are
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
equipped with
PIN CONNECTION AND IEC LOGIC SYMBOLS
ORDER CODES :
74ACT280B
74ACT280M
M
(Micro Package)
B
(Plastic Package)
1/8
相關(guān)PDF資料
PDF描述
74ACT280B 9 BIT PARITY GENERATOR/CHECKER
74ACT280M 9 BIT PARITY GENERATOR/CHECKER
74ACT299 18-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceivers 56-TSSOP -40 to 85
74ACT299B 8 BIT PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR
74ACT299M 18-Bit LVTTL-to-GTL/GTL+ Universal Bus Transceivers 56-SSOP -40 to 85
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