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參數(shù)資料
| 型號： | 74ACT899 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 9-Bit Latchable Transceiver with Parity Generator/Checker |
| 中文描述： | 9位鎖存收發(fā)器奇偶發(fā)生器/檢查 |
| 文件頁數(shù)： | 2/14頁 |
| 文件大?。?/td> | 214K |
| 代理商： | 74ACT899 |
Pin Names
Description
A
0
–A
7
B
0
–B
7
APAR, BPAR
ODD/EVEN
A Bus Data Inputs/Data Outputs
B Bus Data Inputs/Data Outputs
A and B Bus Parity Inputs
ODD/EVEN Parity Select, Active
LOW for EVEN Parity
Output Enables for A or B Bus,
Active LOW
Select Pin for Feed-Through or
Generate Mode, LOW for Generate
Mode
Latch Enables for A and B Latches,
HIGH for Transparent Mode
Error Signals for Checking
Generated Parity with Parity In,
LOW if Error Occurs
GBA, GAB
SEL
LEA, LEB
ERRA, ERRB
Functional Description
The ’AC/’ACT899 has three principal modes of operation
which are outlined below. These modes apply to both the A-
to-B and B-to-A directions.
D Bus A (B) communicates to Bus B (A), parity is generat-
ed and passed on to the B (A) Bus as BPAR (APAR). If
LEB (LEA) is HIGH and the Mode Select (SEL) is LOW,
the parity generated from B
[
0:7
]
(A
[
0:7
]
) can be
checked and monitored by ERRB (ERRA).
D Bus A (B) communicates to Bus B (A) in a feed-through
mode if SEL is HIGH. Parity is still generated and
checked as ERRA and ERRB in the feed-through mode
(can be used as an interrupt to signal a data/parity bit
error to the CPU).
D Independent Latch Enables (LEA and LEB) allow other
permutations of generating/checking (see Function Ta-
ble below).
Function Table
Inputs
Operation
GAB
GBA
SEL
LEA
LEB
H
H
X
X
X
Busses A and B are TRI-STATE
é
.
Generates parity from B
[
0:7
]
based on O/E (Note 1). Generated parity
APAR. Generated parity checked against BPAR and output as
ERRB.
Generates parity from B
[
0:7
]
based on O/E. Generated parity
x
APAR. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check
as ERRA.
H
L
L
L
H
H
L
L
H
H
H
L
L
X
L
Generates parity from B latch data based on O/E. Generated parity
APAR. Generated parity checked against latched BPAR and
output as ERRB.
BPAR/B
[
0:7
]
x
APAR/A0:7
]
Feed-through mode. Generated parity
checked against BPAR and output as ERRB.
BPAR/B
[
0:7
]
x
APAR/A
[
0:7
]
Feed-through mode. Generated parity checked against BPAR and
output as ERRB. Generated parity also fed back through the A latch for
generate/check as ERRA.
Generates parity for A
[
0:7
]
based on O/E. Generated parity
x
BPAR. Generated parity checked against APAR and output as ERRA.
Generates parity from A
[
0:7
]
based on O/E. Generated parity
x
BPAR. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check
as ERRB.
H
L
H
X
H
H
L
H
H
H
L
H
L
H
L
L
H
L
H
H
L
H
L
L
X
Generates parity from A latch data based on O/E. Generated parity
BPAR. Generated parity checked against latched APAR and
output as ERRA.
APAR/A
[
0:7
]
x
BPAR/B
[
0:7
]
Feed-through mode. Generated parity checked against APAR and
output as ERRA.
APAR/A
[
0:7
]
x
BPAR/B
[
0:7
]
Feed-through mode. Generated parity checked against APAR and
output as ERRA. Generated parity also fed back through the B latch for
generate/check as ERRB.
L
H
H
H
L
L
H
H
H
H
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Note 1:
O/E
e
ODD/EVEN
2
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